Xilinx Webpack 9.1i.03 Verilog synthesis bug?

[Xilinx user]

For the combinational-logic of my state-machine, if I use an always @*,
Xilinx XST erroneously optimizes/removes the logic, and then rips out
any downstream load-logic.

reg [6:0] s_instr_category;

// The "BAD" state-machine
always @* begin : state_machine // <-- line #461
if ( a00 ) s_instr_category = A;
else if ( a01 ) s_instr_category = B;
else if ( a02 ) s_instr_category = C;
...
else
s_instr_category = MY_DEFAULT;
end // always @*

always @ (posedge clk )
if ( s_instr_category == A )
decision_junk <= s;
else if (s_instr_category == B )
decision_junk <= s + 1;
...


WARNING:Xst:905 - "control_fsm.v" line 461: The signals <s_instr_category>
are missing in the sensitivity list of always block.
Module <control_fsm> is correct for synthesis.

I've tried changing always @* -> always @ ( a00,a01,a02,...), but I always
see the same WARNING in the logfile.
I've worked around this problem by using the ?: operator. For some reason,
Xilinx XST is perfectly happy with the following-code (but not the code I
posted top.)

wire [6:0] s_instr_category;

// The "BAD" state-machine
assign s_instr_category =
(a00) ? A :
(a01) ? B :
(a02) ? C :
...
: MY_DEFAULT;

....
Any ideas? I'm using Webpack 9.1i with Service Pack 3 (and IP-update 2.1)
Will this be fixed in Webpack 9.2?
And using 2D-regs in an always @* block still doesn't work.

reg [15:0] mem [0:255];
wire [7:0] address;

always @*
latch_dout = mem[ address ]; // <-- XST 9.1i.03 *ERROR*