Xilinx warning for DCM

[srini]

Hi,
I am using a DCM in VirtexII which takes a 20 Mhz input and generates a
60 Mhz output.
I am synthesizing using Synplify Pro and using Xilinx ISE 7.1 for PAR.
After PAR, I am getting a warning that the CLKO output from the DCM is
less than 24 MHz. I know that the min. output freq. from the DCM should
be 24 Mhz. In my case, I am getting a 60 MHz output from the CLKFX pin
of the DCM and I am not using the CLKO pin. So, I would like to know
whether this warning will create some problem in the timing of the
clocks in the design.

Thanks & Regards,
Srini.

 

[John_H]

srini wrote:

Hi,
I am using a DCM in VirtexII which takes a 20 Mhz input and generates a
60 Mhz output.
I am synthesizing using Synplify Pro and using Xilinx ISE 7.1 for PAR.
After PAR, I am getting a warning that the CLKO output from the DCM is
less than 24 MHz. I know that the min. output freq. from the DCM should
be 24 Mhz. In my case, I am getting a 60 MHz output from the CLKFX pin
of the DCM and I am not using the CLKO pin. So, I would like to know
whether this warning will create some problem in the timing of the
clocks in the design.

Thanks & Regards,
Srini.

If you're just using the CLKFX outputs your input can go down to 1 MHz.
Are you using the CLK0 feedback to align your CLKFX output to your
input clock edge? It's this operation that might be unsupported over
all silicon operating ranges. You can generate just the CLKFX with no
feedback well below the 24 MHz but you don't get the deskew.

If you need the alignment, you might ask a more detailed question on
comp.arch.fpga where some Xilinx apps engineers who know the DCMs from
all aspects can help flesh out the nuances.

- John_H