J
jc
Guest
I have a input signal thats get registered and then outputed on
another signal (pad) One register delay. I would like the Output
register to used instead of the Input register. I am using Xilinx ISE,
VHDL and a Virtex II device. Everytime I implement the Input register
is used, how do I use the Output register. I am trying to improve the
clock to pad time.
Thanks
John C
another signal (pad) One register delay. I would like the Output
register to used instead of the Input register. I am using Xilinx ISE,
VHDL and a Virtex II device. Everytime I implement the Input register
is used, how do I use the Output register. I am trying to improve the
clock to pad time.
Thanks
John C