D
Denis
Guest
It seems I have a strange problem with my timing constraints, I have
recently generated a tsi report using the xilinx trace tool(using ISE
5.2),
trce -tsi file.tsi file.ncd file.pcf -v 5 -u 5 -skew -o file.v.twr
The report states that a considerable number of nets in our design
fall under the constraint "Unconstrained path analysis". We have
multiple clock domains in our design so I initially assumed that the
unconstrained nets would be on the synchronisation buffers (which
might not be completely covered by the period constraints we have
assigned for all of our clocks), however when I checked the offending
nets I found that many reffered to FFS whose input and output
connections were all on the same clock domain. I am unsure at this
stage how these nets got into the unconstrained section as their
inputs and outputs only feed FFS on the same domain.
The reason this is a problem is that there is a constraints
intersection issue between the unconstrained section and my other
constraints.
Denis
recently generated a tsi report using the xilinx trace tool(using ISE
5.2),
trce -tsi file.tsi file.ncd file.pcf -v 5 -u 5 -skew -o file.v.twr
The report states that a considerable number of nets in our design
fall under the constraint "Unconstrained path analysis". We have
multiple clock domains in our design so I initially assumed that the
unconstrained nets would be on the synchronisation buffers (which
might not be completely covered by the period constraints we have
assigned for all of our clocks), however when I checked the offending
nets I found that many reffered to FFS whose input and output
connections were all on the same clock domain. I am unsure at this
stage how these nets got into the unconstrained section as their
inputs and outputs only feed FFS on the same domain.
The reason this is a problem is that there is a constraints
intersection issue between the unconstrained section and my other
constraints.
Denis