Xilinx "This design element is inferred rather than instanti

[Nevo]

I'm brand new to FPGA's and Verilog, so I beg your patience.

I'm planning my first design on a Xilinx FPGA and am writing the
project in Verilog.

The Xilinx unified libraries contain a number of useful building blocks
such as counters, shift registers, etc. If I were designing my project
with a schematic source file, I could drag-and-drop the library symbols
to get the functionality of those elements in my project.

However, I can't figure out how to get those elements in my project
when writing the project in Verilog.

Can anyone tell me the 'right' way to do this? I assume it's a simply
matter of linking my project to the vendor's library, but the actual
implementation/steps to do this elude me.

Thanks,

-Nevo

 

[PeterSmith1954@googlemail]

Nevo wrote:

I'm brand new to FPGA's and Verilog, so I beg your patience.

I'm planning my first design on a Xilinx FPGA and am writing the
project in Verilog.

The Xilinx unified libraries contain a number of useful building blocks
such as counters, shift registers, etc. If I were designing my project
with a schematic source file, I could drag-and-drop the library symbols
to get the functionality of those elements in my project.

However, I can't figure out how to get those elements in my project
when writing the project in Verilog.

Can anyone tell me the 'right' way to do this? I assume it's a simply
matter of linking my project to the vendor's library, but the actual
implementation/steps to do this elude me.

Thanks,

-Nevo

Hi Nevo


This article at Xilinx
http://toolbox.xilinx.com/docsan/xilinx8/help/iseguide/html/ise_imp_instantiation_and_inference.htm

has a huge amount of information about the process.

Read and play with the process, then ask some more

Cheers

PeteS

 

[RobJ]

"Nevo" <nevo_n@hotmail.com> wrote in message
news:1154117741.868714.166270@i42g2000cwa.googlegroups.com...

I'm brand new to FPGA's and Verilog, so I beg your patience.

I'm planning my first design on a Xilinx FPGA and am writing the
project in Verilog.

The Xilinx unified libraries contain a number of useful building blocks
such as counters, shift registers, etc. If I were designing my project
with a schematic source file, I could drag-and-drop the library symbols
to get the functionality of those elements in my project.

However, I can't figure out how to get those elements in my project
when writing the project in Verilog.

Can anyone tell me the 'right' way to do this? I assume it's a simply
matter of linking my project to the vendor's library, but the actual
implementation/steps to do this elude me.

Thanks,

-Nevo

The Xilinx tools will recognize the primitive names without you having to do

anything. You just have to instantiate them correctly in your verilog code
(see the Xilinx libraries guide). For simulation you have to map the
libraries so your simulator know where to find them. In the case of Modelsim
you have to compile the libraries and then map the compiled version. Xilinx
provides a script called "compxlib" that does the compiling for you, or I
think you can also download the compiled libs. Read the Xilinx "Synthesis
and Simulation Design Guide" document.

Rob

 

[General Schvantzkoph]

On Fri, 28 Jul 2006 13:15:42 -0700, Nevo wrote:

I'm brand new to FPGA's and Verilog, so I beg your patience.

I'm planning my first design on a Xilinx FPGA and am writing the
project in Verilog.

The Xilinx unified libraries contain a number of useful building blocks
such as counters, shift registers, etc. If I were designing my project
with a schematic source file, I could drag-and-drop the library symbols
to get the functionality of those elements in my project.

However, I can't figure out how to get those elements in my project
when writing the project in Verilog.

Can anyone tell me the 'right' way to do this? I assume it's a simply
matter of linking my project to the vendor's library, but the actual
implementation/steps to do this elude me.

Thanks,

-Nevo

There is a user's guide for the synthesis tool that you are using, XST,
Synplify, or Precision. That user's guide will give you templates that
you should follow to get the synthesis tool to infer various components.
Not all components can be inferred and you may prefer to explicitly
instantiate some components even if they can be inferred because that will
allow you to simulate them using the Xilinx models. There is a library of
components in $XILINX/verilog/src/unisims. You can directly instantiate
these components in your Verilog just as you would your own modules.