Xilinx System Generator

[Timo Dammes]

Hello

I'd like to use Xilinx System Generator (Matlab Simulink tool) to configure
a Xilinx fpga : (Spartan 2, Xc2s200) for a practical course at university.

If anyone has experiences with System Generator :
Is it possible to access the memory of the fpga with a block ? I wrote a c++
program that transfers data (i.e. a picture) to the fpga's memory. Then I'd
like the System Generator schematic to read that data, work with it and
write it back to the memory. Is that possible with the "single port ram"
block ?

Does anyone already have an example program ?

Regards,
Timo Dammes

 

[Jianyong Niu]

Hi, Timo,
A single port ram works in your case, but make sure you dont overwrite the
original data before they are processed. I put a bit algorithm here for your
ref.

in a typical loop,,
1>generate an address
2>set read signal
3>process the data shown at the output port of the ram block using the
sysgen block
4>set ram write signal (write the result to the same address of the original
data in the ram)
then start another loop..

jy


"Timo Dammes" <timo.dammes@gmx.de> wrote in message
news:c97fbf$d6j$1@nx6.HRZ.Uni-Dortmund.DE...

Hello

I'd like to use Xilinx System Generator (Matlab Simulink tool) to
configure
a Xilinx fpga : (Spartan 2, Xc2s200) for a practical course at
university.

If anyone has experiences with System Generator :
Is it possible to access the memory of the fpga with a block ? I wrote a
c++
program that transfers data (i.e. a picture) to the fpga's memory. Then
I'd
like the System Generator schematic to read that data, work with it and
write it back to the memory. Is that possible with the "single port ram"
block ?

Does anyone already have an example program ?

Regards,
Timo Dammes