Y
Yttrium
Guest
Hey,
i'm trying out some stuff in the Xilinx System Generator and i got some
errors during translation
ERROR:NgdBuild:604 - logical block 'streamingfft_fft_fft64a_fft64a' with
type
'vfft64v2' could not be resolved. A pin name misspelling can cause this,
a
missing edif or ngc file, or the misspelling of a type name. Symbol
'vfft64v2' is not supported in target 'virtex2'.
the strangest thing is that when i check in the synthesis report nothing
strange arises and no pin name misspelling has occured. i also tried some of
the aswers on the support site (like disabling read cores and giving a
specific macro search path) but they don't seem to work.... the only thing i
found is that of these components of the design there aren't any edn files?
might that be the problem and how could i make XSG or XST generate them? (i
have tried running XSG regenerating the same design and always the same
problem)
thanx in advance,
kind regards,
Yttrium
i'm trying out some stuff in the Xilinx System Generator and i got some
errors during translation
ERROR:NgdBuild:604 - logical block 'streamingfft_fft_fft64a_fft64a' with
type
'vfft64v2' could not be resolved. A pin name misspelling can cause this,
a
missing edif or ngc file, or the misspelling of a type name. Symbol
'vfft64v2' is not supported in target 'virtex2'.
the strangest thing is that when i check in the synthesis report nothing
strange arises and no pin name misspelling has occured. i also tried some of
the aswers on the support site (like disabling read cores and giving a
specific macro search path) but they don't seem to work.... the only thing i
found is that of these components of the design there aren't any edn files?
might that be the problem and how could i make XSG or XST generate them? (i
have tried running XSG regenerating the same design and always the same
problem)
thanx in advance,
kind regards,
Yttrium