Xilinx Synthesis, Top Level missing a Block in schematic

[Mirza.AR]

Hi all,
I am beginnner level to Xilinx ISE tool as well as verilig.

I have six bloks and one top level Module in a design, I synthesis, it
went all ok excepts some warnings which are related to some of the
latches.

when i check the RTL Schematic, I could not find one of the module i
develoed no idea why is it like this.
my top level code is pasted here;

`include "twdetect.v" file and module name is detect_tw is not found
in top level rtl diagram.

/
********************************************************************************

ERROR DETECTION MODULE VERIFICATION OF DATA TRANSLITTED BY SYSTEC

*********************************************************************************

TOP LEVEL OF ERROR DETECTION MODULE
FILE: er_dt_top.v
DATE: 11/03/2007

********************************************************************************/
/*
`include "test_ch_add.v"
`include "blk_length_comp.v"
`include "bus.v"
`include "count.v"
`include "fsm.v"
`include "twdetect.v"*/

/
*******************************************************************************/


module
err_detect(clk,rst,din,blk_len,alt_ch_add,mem_no,mem_rd,add_out,stat_reg,ts_err);


input clk,rst,mem_rd;

input [39:0] din;
input [9:0] blk_len;
input [9:0] alt_ch_add;
input [1:0] mem_no;

output [4:0] stat_reg;
output [9:0] ts_err;
output [9:0] add_out;


/* here the needed wires and regs will be declared once all the
compnents are added in this description */

wire rd_nxt,nxt_clust,ch_add_err,bl_err;


// reg [4:0] stat_reg;
// reg [9:0] ts_err;
// reg [9:0] add_out;


// State Machine Instantiation
fsm_err_det st_machine
(clk,rst,mem_rd,eod,twd,eob,ch_add_err,bl_err,time_err,reset,ld, shft,
rd_nxt,nxt_clst,ld_trwd,ld_bl_ch,ld_cw,stat_reg);

// to detect the trailer word and end of data "2AAA' and "2AA"
twdetect trl_wrd_det(data,EOB,TWD);

// to verify the channel address from trailer word and RL
memory
address_comp add_comp(RCU_add, TW_add,ch_add_err);

// to verify the Number of 10bit words and locations indicated by
memory pointer
BL_comp blk_len_chk(reset,blok_len, tw_no_bit,bl_err,
cw_pos);

// Data Bus to transfer the data to and from different blocks
bus
data_bus(clk,reset,din,shft,ld,cw_pos,ld_trwd,ld_bl_ch,ld_cw,dout1,
dout2,tr_wd );

// counter for address counter
counter add_count
(clk,reset,rd_nxt,add_in,nxt_clust,jump_ts,nxt_cw,add_out);

// time stamp and cluster width verification
ts_verify time_verify(ts,cw,reset,time_err,ts_err,jump);


// connections to the trailer word etection module

assign data = (ld_trwd == 1)? tr_wd : 14'b00000000000000;
assign twd = TWD;
assign eob = EOB;

// connections to the channel address from trailer word and RL
memory CH address test module

assign TW_add = (ld_bl_ch == 1)? dout2 : 10'b0000000000;
assign RCU_add = alt_ch_add;
assign ch_add_err = ch_add_err;

// connections to Number of 10bit words and locations indicated by
memory pointer test module

assign tw_no_bit = (ld_bl_ch == 1)? dout1 : 10'b0000000000;
// assign blk_len = blok_len;
assign bl_err = bl_err;
assign cw_pos = cw_pos;

// connections to counter for address counter module

assign jump_ts = (nxt_clst == 1)? jump : 10'b0000000000;
assign add_in = blk_len;
assign rd_nxt = rd_nxt;
assign nxt_clst = nxt_clst;
assign cw_pos = cw_pos;
// assign add_out = add_out;

// connections to time stamp and cluster width verification module

assign cw = (ld_cw == 1)? dout1 : 10'b0000000000;
assign ts = (ld_cw == 1)? dout1 : 10'b0000000000;
assign rd_nxt = rd_nxt;
assign nxt_clust = nxt_clst;
assign cw_pos = cw_pos;



endmodule
*****************************************************************************************

please advise me; if I am not clear enough to state the problem please
let me guide me.

best regards and thanks for your time;

mirza