Xilinx support makes me want to scream

[ghelbig]

Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR. The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support: "Your design fails PAR
with ISE-12, can you help ..."

Sigh. Heavy sigh.

Thanks for listening,
G.

 

[Brian Drummond]

On Wed, 15 Dec 2010 08:59:41 -0800 (PST), ghelbig <ghelbig@lycos.com> wrote:

Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR. The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support: "Your design fails PAR
with ISE-12, can you help ..."

Sigh. Heavy sigh.

So... congratulate them on reproducing the problem, and ask when they expect to
have a solution!

- Brian

 

[Chris Maryan]

Perhaps in an effort to solve your problem faster than Xilinx support: how is it failing? Is it a timing failure (i.e. a normal PAR failure)?

If so, that's not unusual between tool versions, especially on designs that are near the limits of the FPGA. The algorithms change between versions and something that formerly passed may not pass anymore. Usually the trade-off is that newer versions will be faster, more robust, and generally better for 90% of designs. You just happen to be in the other 10% this time.

Tweak your constraints, add area groups where necessary and do whatever you would normally do to get a design to pass PAR.

The fact that you passed PAR before is only valid for a given set of constraints, netlist and tool (ISE 11.5). This also underscores the importance of specifying the toolchain along with any source code control tags if you need to have (and everyone should need to have) completely repeatable bit files.

Chris

 

[ghelbig]

On Dec 15, 12:13 pm, Chris Maryan <kmar...@gmail.com> wrote:

Perhaps in an effort to solve your problem faster than Xilinx support: how is it failing? Is it a timing failure (i.e. a normal PAR failure)?

If so, that's not unusual between tool versions, especially on designs that are near the limits of the FPGA. The algorithms change between versions and something that formerly passed may not pass anymore. Usually the trade-off is that newer versions will be faster, more robust, and generally better for 90% of designs. You just happen to be in the other 10% this time.

Tweak your constraints, add area groups where necessary and do whatever you would normally do to get a design to pass PAR.

The fact that you passed PAR before is only valid for a given set of constraints, netlist and tool (ISE 11.5). This also underscores the importance of specifying the toolchain along with any source code control tags if you need to have (and everyone should need to have) completely repeatable bit files.

Chris

It looks like I wasn't communicating properly: their reply made it
seem that they wanted my help getting it to pass PAR. Or that even
though it worked in 11.5, it was a user design error that caused MAP
to pass an invalid placement to PAR. (AFAIK, in v12 'place' is done
by MAP, and PAR is just a router.)

It doesn't start as a timing failure. MAP puts hard macros where they
can't go (too far away from their dedicated I/O pins), and PAR
generates an error instead of moving them. Version 11 always puts
these blocks in the one and only place that they will fit.

When I constrain them to where they must be (and where v11 puts them
without LOC constraints) is when the timing error surfaces. Both
versions fail timing when these blocks have LOC constraints. Version
11 does NOT fail timing when the blocks are placed w/o LOC, even
though (w/ v11) all of these blocks are in exactly the same place with
or without LOC constraints. Obviously I couldn't try v12 w/o the
LOCs.

G.

 

[Marc Jet]

Looks like you were testing the limits of v11 already.

I'd try to LOC a different small component (something like a single
FF) prominently where v12 wants to place your hard macro. That should
force v12 to choose a different placement. Rinse & repeat until the
macro ends up where it needs to be.

Not a good solution, but maybe enough to make it work until a real fix
is found. Good luck!

 

[MM]

You might want trying to run multiple strategies using either PlanAhead
and/or SmartXplorer. I've been playing with these tools recently and found
them to be quite useful. The way I used them was to first find the best
working implementation strategy with PlanAhead (and some strategies would
fail completely) and then cycle that particular strategy through
SmartXplorer while changing just the seed. Again, I found that some seeds
would make the MAP fail completely, while others would produce an order of
magnitude different timing scores.

/Mikhail



"ghelbig" <ghelbig@lycos.com> wrote in message
news:f56c2c16-a18b-4c18-a09f-2b0f1620b94f@a28g2000prb.googlegroups.com...

Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR. The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support: "Your design fails PAR
with ISE-12, can you help ..."

Sigh. Heavy sigh.

Thanks for listening,
G.

 

[jt_eaton]

Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR. The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support: "Your design fails PAR
with ISE-12, can you help ..."

Sigh. Heavy sigh.

Thanks for listening,
G.

Are you paying for support? If you don't like Xilinx support then you ca
switch to Altera's.

One of the big complaints about Open Source Software is that there is n
sure path to finding a solution to your problems. In the EDA world close
source software is not much better.

You have to think of fpgas like you are writing software that must fit int
a fixed size rom chip. If your code is one byte over then the tool wil
fail. You need to understand how your code maps into fpga logic and wher
the critical timing paths occur. It looks like you design was on the brin
and any slight algorithm change could push it over. Try compiling for
larger part or a slower speed. Look for long chains of combinational logi
and try to pipeline them

John Eaton



---------------------------------------
Posted through http://www.FPGARelated.com

 

[Mawa_fugo]

On Dec 15 2010, 10:59 am, ghelbig <ghel...@lycos.com> wrote:

Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR.  The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support:  "Your design fails PAR
with ISE-12, can you help ..."

Sigh.  Heavy sigh.

Thanks for listening,
G.

Xilinx bugs always make my feet cold

 

[Mawa_fugo]

On Dec 22 2010, 1:01 pm, "MM" <mb...@yahoo.com> wrote:

You might want trying to run multiple strategies using either PlanAhead

He can joint the beatAhead team to solve the problem

 

[Symon]

On 12/15/2010 4:59 PM, ghelbig wrote:

Sorry, but I need to vent.

I have a design that works just fine with ISE-11.5, and fails 'PAR'
with ISE-12.3

I opened a web case about my design failing PAR. The archive of the
project created with ISE was incomplete, so it has taken a while (six
weeks) to get all of the files transferred.

I just got an email from Xilinx Tech Support: "Your design fails PAR
with ISE-12, can you help ..."

Sigh. Heavy sigh.

Thanks for listening,
G.

If you think designing with their parts is bad, you should try logging
onto glassdoor.com and find out what people who claim to be employees
think of working at the place.

Syms.