xilinx spartan3e clock domain crossing or synchronizing two

[Arne]

Hello,

following situation:

I have a board with a 10MHz oscillator which supplies a microcontroller and a spartan3e.

The spartan uses a DCM to generate 50MHz for a global clock.
The Controller has also a PLL to generate 50Mhz internal.

Both, the controller and the spartan are connected over a parallel bus, the bus interface has a
clock output (configured to 50MHz, permanently on).
These clock signal is connected to a LHCLK input of the spartan.

The simplest way for me would be to use the supplied bus clock at LHCLK-Pin as global clock for my
design, but I get warnings when I try this.
I can't feed a DCM with a LHCLK signal, at least I wasn't able to do this.

Because the clocks have the same source, I could try to synchronize them.
I tried to use the bus clock as feedback for the DCM, but when I Try this
I get errormessages like "Place:1012 - A clock IOB / DCM component pair have been found that are not
placed at an optimal clock IOB / DCM site pair."

Another solution I think about is to use the bus clock to feed the bus-interface and then building a
fifo for clock domain crossing, but this is more complex.

Any suggestion what would be the best way to solve this problem?

regards
Arne

 

[Gabor]

On Oct 23, 8:14 am, Arne <a...@pagelnet.de> wrote:

Hello,

following situation:

I have a board with a 10MHz oscillator which supplies a microcontroller and a spartan3e.

The spartan uses a DCM to generate 50MHz for a global clock.
The Controller has also a PLL to generate 50Mhz internal.

Both, the controller and the spartan are connected over a parallel bus, the bus interface has a
clock output (configured to 50MHz, permanently on).
These clock signal is connected to a LHCLK input of the spartan.

The simplest way for me would be to use the supplied bus clock at LHCLK-Pin as global clock for my
design, but I get warnings when I try this.
I can't feed a DCM with a LHCLK signal, at least I wasn't able to do this..

Because the clocks have the same source, I could try to synchronize them.
I tried to use the bus clock as feedback for the DCM, but when I Try this
I get errormessages like "Place:1012 - A clock IOB / DCM component pair have been found that are not
placed at an optimal clock IOB / DCM site pair."

Another solution I think about is to use the bus clock to feed the bus-interface and then building a
fifo for clock domain crossing, but this is more complex.

Any suggestion what would be the best way to solve this problem?

regards
   Arne

For use with a DCM you should really place the clock on a global (GC)
clock pin
rather than a side clock. However you can still force the design to
route with the
less optimal clocking connection. If you read the rest of the error
message it
should have a line that shows exactly what to place in your .ucf file
to override
the error and demote it to a warning. The down side of this is that
you will get
a fairly large delay in the path from the clock pin to the DCM (that's
why they
don't recommend this and make it an error by default). Perhaps a
better option
is to use the clock without a DCM. At 50 MHz, you might find this
option is
still good enough to meet timing. Assuming any IOB's that need to run
on this
clock are on the same half of the chip ("left" side as suggested by
the name
LHCLK), then this should prevent the errors. If you use IOB flip-
flops for
sampling the bus signals, you may need to instantiate IDELAY elements
to reduce the hold time requirement to zero. This was the default
for earlier devices, so I'm not sure if you need this for Spartan 3E
or not.
Also if you don't specify a clock buffer, the tools should insert a
regional
clock buffer by default. If not you may need to instantiate a BUFR on
this instead of BUFG.

Definitely add OFFSET IN timing constraints to your .ucf file to make
sure the clocking scheme is adequate.

HTH,
Gabor

 

[d_s_klein]

On Oct 23, 5:14 am, Arne <a...@pagelnet.de> wrote:

Hello,

following situation:

I have a board with a 10MHz oscillator which supplies a microcontroller and a spartan3e.

The spartan uses a DCM to generate 50MHz for a global clock.
The Controller has also a PLL to generate 50Mhz internal.

Both, the controller and the spartan are connected over a parallel bus, the bus interface has a
clock output (configured to 50MHz, permanently on).
These clock signal is connected to a LHCLK input of the spartan.

The simplest way for me would be to use the supplied bus clock at LHCLK-Pin as global clock for my
design, but I get warnings when I try this.
I can't feed a DCM with a LHCLK signal, at least I wasn't able to do this..

Because the clocks have the same source, I could try to synchronize them.
I tried to use the bus clock as feedback for the DCM, but when I Try this
I get errormessages like "Place:1012 - A clock IOB / DCM component pair have been found that are not
placed at an optimal clock IOB / DCM site pair."

Another solution I think about is to use the bus clock to feed the bus-interface and then building a
fifo for clock domain crossing, but this is more complex.

Any suggestion what would be the best way to solve this problem?

regards
   Arne

You will never get the two 50MHz clocks to synchronize.

If it were me, I would ignore the 10MHz into the FPGA, and use the
50MHz from the controller for _everything_.

RK