I
itsme
Guest
Hi all,
I am actually trying to switch a virtex2 project to spartan3. While
implementing the design I got several timing errors. One reason is that the
timing parameter "CLK to valid Data on Pad" (Tiockon). The data sheet of
virtex2 gives a value of 3.51ns. The value for spartan3 is 5.865ns - which
is much higher!!! . I got this value for spartan3 from Timing Analyzer
(Vers. 6.1.03i). In the newest datasheet of the spartan3 the chapter
"switching characteristics" is still quite empty.
So I really wonder what the XILINX guys do. Selling a chip without timing
specs? Is the spartan3 really much slower than the Virtex2?
Any comments? Any Spartan3 Users?
I am actually trying to switch a virtex2 project to spartan3. While
implementing the design I got several timing errors. One reason is that the
timing parameter "CLK to valid Data on Pad" (Tiockon). The data sheet of
virtex2 gives a value of 3.51ns. The value for spartan3 is 5.865ns - which
is much higher!!! . I got this value for spartan3 from Timing Analyzer
(Vers. 6.1.03i). In the newest datasheet of the spartan3 the chapter
"switching characteristics" is still quite empty.
So I really wonder what the XILINX guys do. Selling a chip without timing
specs? Is the spartan3 really much slower than the Virtex2?
Any comments? Any Spartan3 Users?