xilinx spartan 6

[Serkan]

I need to route a FAST CLK (that is used for deserializing and input
to only one bank) to another bank's IODELAY2 and IOSERDES2 elements.
Is this possible?

Please remember that I also need to send signals like,

-serdesstrobe,
-fast ioclk(sampling fast serial data),
-parallel clk(clk whose frequency is the same as parallel
data(deserialized data)) to these elements.

Serkan

 

[Ed McGettigan]

On Feb 28, 7:56 am, Serkan <ok...@su.sabanciuniv.edu> wrote:

I need to route a FAST CLK (that is used for deserializing and input
to only one bank) to another bank's IODELAY2 and IOSERDES2 elements.
Is this possible?

Please remember that I also need to send signals like,

-serdesstrobe,
-fast ioclk(sampling fast serial data),
-parallel clk(clk whose frequency is the same as parallel
data(deserialized data)) to these elements.

Serkan

This isn't possible. These clocks can only operate within one bank.

You may be able to just use a BUFG if the data rate isn't too high.

Ed McGettigan
--
Xilinx Inc.

 

[Serkan]

On Mar 1, 6:26 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Feb 28, 7:56 am, Serkan <ok...@su.sabanciuniv.edu> wrote:

I need to route a FAST CLK (that is used for deserializing and input
to only one bank) to another bank's IODELAY2 and IOSERDES2 elements.
Is this possible?

Please remember that I also need to send signals like,

-serdesstrobe,
-fast ioclk(sampling fast serial data),
-parallel clk(clk whose frequency is the same as parallel
data(deserialized data)) to these elements.

Serkan

This isn't possible.  These clocks can only operate within one bank.

You may be able to just use a BUFG if the data rate isn't too high.

Ed McGettigan
--
Xilinx Inc.

Dear Ed,

Are you sure about this?

Because I could be able to drive two PLLs with BUFIO2s using two
ISERDES(DFB) outputs.
Maybe I'm missing something but below config placed and routed.

same GCLK --> same IBUFGDS-->first ISERDES2(DFB)==>first bufio2===>
PLL 1
same GCLK --> same IBUFGDS-->2nd ISERDES2(DFB)==>2nd bufio2===> PLL 2

I'm trying to do this because I do not want to be limited to 400Mhz of
Spartan 6 BUFGs while deserializing.