S
Serkan
Guest
I just have 1 fast LVDS data line. I need to have 10 bits of data
in a register , every 5 clock cycles(DDR), coming from only 1
differential data line.
Dear Gurus,
1- Can I deserialize a 240 Mhz , LVDS, DDR input coming data using a
10:1 serdes ratio. (clk is also LVDS)
2- I want to do it with data width = 1( D = 1), is it possible?
3- Do I have to put delay to clk inputs. If not why is there a delay
element (IODELAY2) in xapp1064.pdf
4- Do I have to use the pll concept. Is there any other solution?
5- In the documentation of spartan 6 deserialization 16:1 is shown
but with a SDR rate. Can it be changed to DDR?
=================================================================
PS1: I am using Spartan 6, slx100, -3
PS2: I checked xapp1064.pdf, ug381.pdf, ds162.pdf. I need more info
on IODELAY2 and ISERDES2.
best regards
Serkan
in a register , every 5 clock cycles(DDR), coming from only 1
differential data line.
Dear Gurus,
1- Can I deserialize a 240 Mhz , LVDS, DDR input coming data using a
10:1 serdes ratio. (clk is also LVDS)
2- I want to do it with data width = 1( D = 1), is it possible?
3- Do I have to put delay to clk inputs. If not why is there a delay
element (IODELAY2) in xapp1064.pdf
4- Do I have to use the pll concept. Is there any other solution?
5- In the documentation of spartan 6 deserialization 16:1 is shown
but with a SDR rate. Can it be changed to DDR?
=================================================================
PS1: I am using Spartan 6, slx100, -3
PS2: I checked xapp1064.pdf, ug381.pdf, ds162.pdf. I need more info
on IODELAY2 and ISERDES2.
best regards
Serkan