Xilinx Rocket IO CRC+Clock Corrections results in CRC error

[Stefan Philipp]

Hi Folks,

I am using the rocket IOs of the Xilinx Virtex II pro chips, with are
working fine, but:

While testing different frequencies in simulation, it seems, that if clock
correction IDLEs
are inserted in data between the SOP/EOP of a CRC checked data package,
this results in an CRC error if clock corrections are needed during readout
of
the receiver elastic buffer, which is not documented in the rocket io user
guide.

This means, that there is no possibility to do any clock correction during
the
receive of crc-checked data and IDLEs could only be transmitted outside the
SOP/EOP.

Does anyone know, if this is generally true ?

Thanks in advance,
Stefan Philipp

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[Marc Randolph]

Stefan Philipp wrote:

Hi Folks,

I am using the rocket IOs of the Xilinx Virtex II pro chips, with are
working fine, but:

While testing different frequencies in simulation, it seems, that if clock
correction IDLEs
are inserted in data between the SOP/EOP of a CRC checked data package,
this results in an CRC error if clock corrections are needed during readout
of
the receiver elastic buffer, which is not documented in the rocket io user
guide.

This means, that there is no possibility to do any clock correction during
the
receive of crc-checked data and IDLEs could only be transmitted outside the
SOP/EOP.

Does anyone know, if this is generally true ?

Howdy Stefan,

"Idle mode [...] occurs during normal operation between frames"
(paraphrased from IEEE). I'm not sure why you'd insert idles in the
middle of a packet (between SOP or EOP), but if you are, don't do that

Also, do you have CLK_COR_KEEP_IDLE set to true? If so, I could see how
that might confuse your CRC checker on the rx side.

Have fun,

Marc