Xilinx : RLOC ORIGIN

[Chris Cheung]

Hi,

Just a stupid question:

I need to implement something in high speed so I have to use RLOC_ORIGIN
statement as some experts suggested.
However, I couldn't find any information regarding to the "which CLB
(x?y?) associate with which output pin".
Does anyone know which Xilinx document to look at for the "addresses"
and phyiscal location of CLBs for certain FPGA? ( I am doing design with
Spartan 3 and Virtex 2 pro).

Thanks

Chris

 

[Marc Baker]

There are various graphical tools to see the association of CLBs to IOBs, such
as PACE, Floorplanner, and FPGA Editor. A straight ASCII file can be generated
by running partgen - for example, "partgen -v 3s200ft256" which creates a
3s200ft256.pkg file.

Chris Cheung wrote:

Hi,

Just a stupid question:

I need to implement something in high speed so I have to use RLOC_ORIGIN
statement as some experts suggested.
However, I couldn't find any information regarding to the "which CLB
(x?y?) associate with which output pin".
Does anyone know which Xilinx document to look at for the "addresses"
and phyiscal location of CLBs for certain FPGA? ( I am doing design with
Spartan 3 and Virtex 2 pro).

Thanks

Chris

--
Marc Baker
Xilinx Applications
(408) 879-5375

 

[Gabor Szakacs]

See also:

http://www.xilinx.com/products/virtex2pro/v2p-pkgs.htm
(for the V2Pro only)

Marc Baker <marc.baker@xilinx.com> wrote in message news:<4044DBC2.D7A5AFA1@xilinx.com>...

There are various graphical tools to see the association of CLBs to IOBs, such
as PACE, Floorplanner, and FPGA Editor. A straight ASCII file can be generated
by running partgen - for example, "partgen -v 3s200ft256" which creates a
3s200ft256.pkg file.

Chris Cheung wrote:

Hi,

Just a stupid question:

I need to implement something in high speed so I have to use RLOC_ORIGIN
statement as some experts suggested.
However, I couldn't find any information regarding to the "which CLB
(x?y?) associate with which output pin".
Does anyone know which Xilinx document to look at for the "addresses"
and phyiscal location of CLBs for certain FPGA? ( I am doing design with
Spartan 3 and Virtex 2 pro).

Thanks

Chris