Xilinx RAM64x1D simulation problems

D

Doug Miller

Guest
When I try to simulate writing into a RAM64x1D, the output (signal "douta")
becomes indeterminate. My testbench file and instantiation file are in the
text that follows. Am I doing something wrong, or is there a problem with
the Xilinx simulation libraries?

Thanks,
Doug

---------------- Cut Here -----------------------------
-- TestBench Template

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_signed.ALL;

library unisim; -- required for Xilinx components instantiated in the design

use unisim.vcomponents.ALL;

ENTITY dp64x1d_tb IS

END dp64x1d_tb;

ARCHITECTURE behavior OF dp64x1d_tb IS

component dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end component;

signal rst : std_logic;

signal clk : std_logic;

signal wr_en : std_logic;

signal in_addr : std_logic_vector(5 downto 0);

signal din : std_logic;

signal douta : std_logic;

signal out_addr : std_logic_vector(5 downto 0) := "000000";

signal doutb : std_logic;

constant CLK100_HALF_PERIOD :time := 5 ns; -- 100 MHz

begin

clk100MHz_proc: process

begin

clk <= '0';

wait for CLK100_HALF_PERIOD;

clk <= '1';

wait for CLK100_HALF_PERIOD;

end process clk100MHz_proc;

generate_some_activity: process(clk,rst)

begin

if (rst = '1') then

in_addr <= (others => '0');

elsif (clk'event and clk = '1') then

if (in_addr /= "111111") then

in_addr <= in_addr + 1;

else

in_addr <= (others => '0');

end if;

end if;

end process;

generate_wr_en: process(clk,rst)

begin

if (rst = '1') then

wr_en <= '0';

elsif (clk'event and clk = '0') then

wr_en <= not rst;

end if;

end process;

din <= in_addr(0) after 1 ns; -- Just put something in there...

-- Component Instantiation

uut: dp64x1d

Port map (

clk => clk,

-- Input Side

wr_en => wr_en,

in_addr => in_addr,

din => din,

douta => douta,

-- Output side

out_addr => out_addr,

doutb => doutb

);



-- ---------------------------------------------------------------

-- Generate the rst pulse

---------------------------------------------------------------

rst_proc: PROCESS

BEGIN

-- Reset the core

rst <= transport std_logic'('1');

WAIT FOR 200 ns;

rst <= transport std_logic'('0');

-- Process the input stimulus data file

WAIT FOR 2 sec;

END PROCESS;

end;

----------------------Cut Here -------------------------------

---------------------------------------------------------------------------

--

-- This is a simple file created to investigate RAM64X1D behavior

--

---------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;

use UNISIM.VComponents.all;

entity dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end dp64x1d;

architecture rtl of dp64x1d is

component RAM64X1D

port (

D : in std_logic;

WE : in std_logic;

WCLK : in std_logic;

A0 : in std_logic;

A1 : in std_logic;

A2 : in std_logic;

A3 : in std_logic;

A4 : in std_logic;

A5 : in std_logic;

DPRA0 : in std_logic;

DPRA1 : in std_logic;

DPRA2 : in std_logic;

DPRA3 : in std_logic;

DPRA4 : in std_logic;

DPRA5 : in std_logic;


SPO : out std_logic;

DPO : out std_logic);

end component;




begin



dp: RAM64X1D

port map (

WCLK => clk,

WE => wr_en,

D => din,

A0 => in_addr(0),

A1 => in_addr(1),

A2 => in_addr(2),

A3 => in_addr(3),

A4 => in_addr(4),

A5 => in_addr(5),

DPRA0 => out_addr(0),

DPRA1 => out_addr(1),

DPRA2 => out_addr(2),

DPRA3 => out_addr(3),

DPRA4 => out_addr(4),

DPRA5 => out_addr(5),


SPO => douta,

DPO => doutb

);

end rtl;

------------------------------- end ---------------------------------
 
OK, just got a little stranger - I ran this at home on my free Xilinx
Edition Modelsim, and it ran fine. At work, I have Modelsim PE, which
generates the indeterminate output. Does this mean that I need to recompile
my Xilinx Unisim library on PE?

Doug


"Doug Miller" <nospam_doug_miller@worldnet.att.net> wrote in message
news:YU5Ac.23866$Di3.5949@bgtnsc05-news.ops.worldnet.att.net...
When I try to simulate writing into a RAM64x1D, the output (signal
"douta")
becomes indeterminate. My testbench file and instantiation file are in
the
text that follows. Am I doing something wrong, or is there a problem with
the Xilinx simulation libraries?

Thanks,
Doug

---------------- Cut Here -----------------------------
-- TestBench Template

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_signed.ALL;

library unisim; -- required for Xilinx components instantiated in the
design

use unisim.vcomponents.ALL;

ENTITY dp64x1d_tb IS

END dp64x1d_tb;

ARCHITECTURE behavior OF dp64x1d_tb IS

component dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end component;

signal rst : std_logic;

signal clk : std_logic;

signal wr_en : std_logic;

signal in_addr : std_logic_vector(5 downto 0);

signal din : std_logic;

signal douta : std_logic;

signal out_addr : std_logic_vector(5 downto 0) := "000000";

signal doutb : std_logic;

constant CLK100_HALF_PERIOD :time := 5 ns; -- 100 MHz

begin

clk100MHz_proc: process

begin

clk <= '0';

wait for CLK100_HALF_PERIOD;

clk <= '1';

wait for CLK100_HALF_PERIOD;

end process clk100MHz_proc;

generate_some_activity: process(clk,rst)

begin

if (rst = '1') then

in_addr <= (others => '0');

elsif (clk'event and clk = '1') then

if (in_addr /= "111111") then

in_addr <= in_addr + 1;

else

in_addr <= (others => '0');

end if;

end if;

end process;

generate_wr_en: process(clk,rst)

begin

if (rst = '1') then

wr_en <= '0';

elsif (clk'event and clk = '0') then

wr_en <= not rst;

end if;

end process;

din <= in_addr(0) after 1 ns; -- Just put something in there...

-- Component Instantiation

uut: dp64x1d

Port map (

clk => clk,

-- Input Side

wr_en => wr_en,

in_addr => in_addr,

din => din,

douta => douta,

-- Output side

out_addr => out_addr,

doutb => doutb

);



-- ---------------------------------------------------------------

-- Generate the rst pulse

---------------------------------------------------------------

rst_proc: PROCESS

BEGIN

-- Reset the core

rst <= transport std_logic'('1');

WAIT FOR 200 ns;

rst <= transport std_logic'('0');

-- Process the input stimulus data file

WAIT FOR 2 sec;

END PROCESS;

end;

----------------------Cut Here -------------------------------

--------------------------------------------------------------------------
-

--

-- This is a simple file created to investigate RAM64X1D behavior

--

--------------------------------------------------------------------------
-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;

use UNISIM.VComponents.all;

entity dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end dp64x1d;

architecture rtl of dp64x1d is

component RAM64X1D

port (

D : in std_logic;

WE : in std_logic;

WCLK : in std_logic;

A0 : in std_logic;

A1 : in std_logic;

A2 : in std_logic;

A3 : in std_logic;

A4 : in std_logic;

A5 : in std_logic;

DPRA0 : in std_logic;

DPRA1 : in std_logic;

DPRA2 : in std_logic;

DPRA3 : in std_logic;

DPRA4 : in std_logic;

DPRA5 : in std_logic;


SPO : out std_logic;

DPO : out std_logic);

end component;




begin



dp: RAM64X1D

port map (

WCLK => clk,

WE => wr_en,

D => din,

A0 => in_addr(0),

A1 => in_addr(1),

A2 => in_addr(2),

A3 => in_addr(3),

A4 => in_addr(4),

A5 => in_addr(5),

DPRA0 => out_addr(0),

DPRA1 => out_addr(1),

DPRA2 => out_addr(2),

DPRA3 => out_addr(3),

DPRA4 => out_addr(4),

DPRA5 => out_addr(5),


SPO => douta,

DPO => doutb

);

end rtl;

------------------------------- end ---------------------------------
Click to expand...
 
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