Xilinx PLB RapidIO LVDS Core

[Kevin Shaw]

Anyone out there using the PLB RapidIO LVDS core in the Xilinx EDK? If so,
have you been able to transmit a packet (NREAD) successfully? I've been able
to successfully complete training mode and the Error and Status CDR shows
the "Port OK" but sending an NREAD packet results in the CSR indicating
"Output Error - Encountered". Any help would be appreciated.

Thanks,

Kevin