Xilinx Platform Flash Prom

P

Pete

Guest
This may be an odd question but here goes...

I would like to use the JTAG chain to program Xilinx's Virtex-II
fpga and the Platform Flash ISP Configuration PROM. OK, that's not a
problem as it's detailed in document DS123 (v2.2). However, I would
like to add a second Platform Flash PROM in the same chain as the
Virtex-II and it's config PROM. This second PROM would be used to
hold general purpose data (ie. not FPGA config data). I would like to
connect this PROM to unused I/O of the FPGA which would then reset the
PROM and pull data out of it serially to be used in other parts of the
product we're developing.

Each "box" we're designing will have analog control bits that need to
be tweaked when the unit is sealed up. The only access I have to the
PROM is through the JTAG interface. I was wondering if anyone has
seen any app notes detailing this sort of interface/design.

Pete
 
Pete wrote:
This may be an odd question but here goes...

I would like to use the JTAG chain to program Xilinx's Virtex-II
fpga and the Platform Flash ISP Configuration PROM. OK, that's not a
problem as it's detailed in document DS123 (v2.2). However, I would
like to add a second Platform Flash PROM in the same chain as the
Virtex-II and it's config PROM. This second PROM would be used to
hold general purpose data (ie. not FPGA config data). I would like to
connect this PROM to unused I/O of the FPGA which would then reset the
PROM and pull data out of it serially to be used in other parts of the
product we're developing.

Each "box" we're designing will have analog control bits that need to
be tweaked when the unit is sealed up. The only access I have to the
PROM is through the JTAG interface. I was wondering if anyone has
seen any app notes detailing this sort of interface/design.

Pete
Click to expand...
Should be straight forward, not much different from using two small
proms to configure one FPGA, except that one of the proms isn't
connected to the configuration pins of the FPGA.

From the JTAG side it'll just be a chain of 2 proms and an FPGA, one
programmed with the fpga configuration the other with you general
purpose data.

The prom connected to the configuration pins on the FPGA configures
the FPGA, the prom connected to I/O's does nothing unless you drive
the pins ..

-Lasse
 
Have you thought of using only one common FlashROM ?
Alternatively, you could use a little 32 kbit EEPROM in an 8-pin minidp,
using a 2-wire interface for reading and writing.
A friend of mine did that, controlled by an FPGA-internal PicoBlaze that
is performing many other control functions already...
Peter Alfke

Lasse Langwadt Christensen wrote:
Pete wrote:
This may be an odd question but here goes...

I would like to use the JTAG chain to program Xilinx's Virtex-II
fpga and the Platform Flash ISP Configuration PROM. OK, that's not a
problem as it's detailed in document DS123 (v2.2). However, I would
like to add a second Platform Flash PROM in the same chain as the
Virtex-II and it's config PROM. This second PROM would be used to
hold general purpose data (ie. not FPGA config data). I would like to
connect this PROM to unused I/O of the FPGA which would then reset the
PROM and pull data out of it serially to be used in other parts of the
product we're developing.

Each "box" we're designing will have analog control bits that need to
be tweaked when the unit is sealed up. The only access I have to the
PROM is through the JTAG interface. I was wondering if anyone has
seen any app notes detailing this sort of interface/design.

Pete

Should be straight forward, not much different from using two small
proms to configure one FPGA, except that one of the proms isn't
connected to the configuration pins of the FPGA.

From the JTAG side it'll just be a chain of 2 proms and an FPGA, one
programmed with the fpga configuration the other with you general
purpose data.

The prom connected to the configuration pins on the FPGA configures
the FPGA, the prom connected to I/O's does nothing unless you drive
the pins ..

-Lasse
Click to expand...
 
Pete,
Have you looked at the schematic for the board,sometimes you might
get a way to access the PROM ;other than that,I dont think it is
possible to access PROM.
I was once trying to do that to load two different config bits and use
them as and when needed, but the solution i got was using System ACE
controller.
you might want to check that out.
Ram
 
"ram" <ramntn@yahoo.com> wrote in message
news:61c2cc9d.0402112133.75b65c0@posting.google.com...
Pete,
Have you looked at the schematic for the board,sometimes you might
get a way to access the PROM ;other than that,I dont think it is
possible to access PROM.
Click to expand...
be smart.
IT IS POSSIBLE to access the (xilinx config) PROM after configuration if you
need it.

Antti
xilinx.openchip.org
 
Lasse Langwadt Christensen <langwadt@ieee.org> wrote in message news:<402AC930.2080307@ieee.org>...
Should be straight forward, not much different from using two small
proms to configure one FPGA, except that one of the proms isn't
connected to the configuration pins of the FPGA.

From the JTAG side it'll just be a chain of 2 proms and an FPGA, one
programmed with the fpga configuration the other with you general
purpose data.

The prom connected to the configuration pins on the FPGA configures
the FPGA, the prom connected to I/O's does nothing unless you drive
the pins ..

-Lasse
Click to expand...
That's pretty much what I was hoping I could do. Now I need to
determine the data format necessary to get the prom configured using
the xilinx supplied tools.

Pete
 
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