Xilinx Place and Route with changing LUT values

[Alan]

Xilinx Virtex II Pro part using version 6.2.02 of the Xilinx Place and
Route tools. The source of the design is an edif file produced by
Leonardo. A complete Place and Route on the device takes approximately 3
hours (2.5G CPU, 2G physical RAM, Win2000)

During an integration (de-bugging) stage for a project I have the need
to quickly change the contents of a Goregen generated memory
look-up-table.

While generating the Gcoregen part I can use a .coe file to define the
contents and this becomes embedded into the resultant Coregen generated
..edn file. However I'm sure that repeatedly re-generating an .edn file
with new values is not the most efficient way to go.

At what stage during the place and route process are the values in .edn
files for Coregen parts used?

More importantly, is there a (relatively) easy and quick way of changing
the values programmed into memory at the back end stage of place and
route, but before the programming file generation stage?

A search of the Xilinx web site always seems to bring up the use of the
..coe (initialisation) file used at the time of Coregen generation but
this surely cannot the way of programming different initial values into
memories when a Goregen memory part is used multiple times within a
design?


--
Alan
mailto:news2me_a_2003@amacleod.clara.co.uk

 

[Brannon King]

Look at the bd option on bitgen. Also, you should be able to use an exact
guide file for the map/par if all else fails.