Xilinx Place and route of a Mixed VHDL-Verilog design

[kb33]

Hi,

I have a Verilog design, which I have instantiated as a component in a
top level VHDL file. The verilog component has the syn_black_box
attribute set, and this whole thing has gone through Synplicity without
any errors (there are warnings, of course).
When I try to place and route the EDF file of the top level design
using a Xilinx Makefile, it is giving me errors. I do keep the
(exclusive) verilog EDF file in the same directory where the EDF file
for the top level design is located (assuming that the P&R tool will
pick up the EDF file of the verilog design on it's own). So what is the
correct procedure for routing such a mixed design on the FPGA? Do I
need to make any changes to the makefile?

Thanks,
kb33