Xilinx PCI Express - Am I starting too low?

S

self

Guest
Hello,

I have used the Xilinx LogiCore Integrated Block for PCI Expres
several times in the past. On those occasions I have hacked into the
autogenerated example design to bring a standard parallel interface up
to the top level for access to registers and block ram. This work has
always been for prototyping and was not really production firmware.
Working this way the PCI Express performance is really low because the
Logicore IP does not support burst transfers or DMA. The software
engineer hacks the linux driver to prevent any PCI Express accesses of
greater than one word so we don't get bus errors.

I just genenerated a version 2.4 AXI4 compatible PCIe core for V6
using ISE 13.3 and I see the design still supports only single word
accesses.

Now we are dong a production design using PCIe and I would like to get
the full performance of the interface. In particular I must support
burst transfers. Ideally I will also provide DMA logic.

Can anyone advise me where to start in order to get where I want to
go?

Am I starting too low using the Xilinx Logicore design?

Does Xilinx provide a better core or reference design with burst
transfer and DMA?

Any advice is greatly appreciated.

Pedro
 
I started out by modifying the base PCIe implementation to accept
multiple DWORD packets, however it turned out that the PCIe root port
in my PC did not support this. You need to implement DMA to get more
performance.

Typing "xilinx pcie dma" into google gave me the following result (you
really should try google next time...) :
Bus Master Performance Demonstration Reference Design for the Xilinx
Endpoint PCI Express Solutions
http://www.xilinx.com/support/documentation/application_notes/xapp1052.pdf

I use this design a great deal, it comes with the required registers
already implemented but not blockram.

Kind regards,
Sam Collinson

On Nov 16, 6:42 am, self <padu...@gmail.com> wrote:
Hello,

I have used the Xilinx LogiCore Integrated Block for PCI Expres
several times in the past. On those occasions I have hacked into the
autogenerated example design to bring a standard parallel interface up
to the top level for access to registers and block ram.  This work has
always been for prototyping and was not really production firmware.
Working this way the PCI Express performance is really low because the
Logicore IP does not support burst transfers or DMA.  The software
engineer hacks the linux driver to prevent any PCI Express accesses of
greater than one word so we don't get bus errors.

I just genenerated a version 2.4 AXI4 compatible PCIe core for V6
using ISE 13.3 and I see the design still supports only single word
accesses.

Now we are dong a production design using PCIe and I would like to get
the full performance of the interface.  In particular I must support
burst transfers.  Ideally I will also provide DMA logic.

Can anyone advise me where to start in order to get where I want to
go?

Am I starting too low using the Xilinx Logicore design?

Does Xilinx provide a better core or reference design with burst
transfer and DMA?

Any advice is greatly appreciated.

  Pedro
Click to expand...
 
If you want DMA you either need to write your own DMA controller or buy
ready made core. Xilinx only provide the PCIe core. I have done this befor
so if you want to contact me I may be able to help you.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Jon,
The application note I posted is a DMA controller provided for free by
Xilinx.
Kind regards,
Sam Collinson

On Nov 20, 9:08 am, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
If you want DMA you either need to write your own DMA controller or buy a
ready made core. Xilinx only provide the PCIe core. I have done this before
so if you want to contact me I may be able to help you.

Jon

---------------------------------------
Posted throughhttp://www.FPGARelated.com
Click to expand...
 
On Sun, 20 Nov 2011 15:41:14 -0800, Sam Collinson wrote:

Jon,
The application note I posted is a DMA controller provided for free by
Xilinx.
Kind regards,
Sam Collinson
Click to expand...
Verilog only, unfortunately.

- Brian
 
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