Xilinx Parallel cable III 3V3 and current impact version?

[Stef]

Hi,

On one of our boards we use a serial (SPI) flash as configuration chip
for a Xilinx spartan3e. We program this memory with the Platform Cable
USB, using the SPI programming mode in impact (ise9.1). This works
fine.

One of these boards is at a remote site and they happen to have an old
parallel cable III available.

Does anyone know if it is possible to program a 3V3 SPI FLASH (M25P16)
using the parallel cable III? Do I need a specific impact version for
this or can I just use the 9.1 or the latest version?


--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

Democracy is a process by which the people are free to choose the man who
will get the blame.
-- Laurence J. Peter

 

[Jon Elson]

On 03/02/2011 10:35 AM, Stef wrote:

Hi,

On one of our boards we use a serial (SPI) flash as configuration chip
for a Xilinx spartan3e. We program this memory with the Platform Cable
USB, using the SPI programming mode in impact (ise9.1). This works
fine.

One of these boards is at a remote site and they happen to have an old
parallel cable III available.

Does anyone know if it is possible to program a 3V3 SPI FLASH (M25P16)
using the parallel cable III? Do I need a specific impact version for
this or can I just use the 9.1 or the latest version?

This should work. I program 3.3 V CPLDs here with no problem using a
parallel cable III. I am now mostly using iSE 10.1 and it seems to work
fine.

Jon

 

[Stef]

In comp.arch.fpga,
Jon Elson <jmelson@wustl.edu> wrote:

On 03/02/2011 10:35 AM, Stef wrote:
Hi,

On one of our boards we use a serial (SPI) flash as configuration chip
for a Xilinx spartan3e. We program this memory with the Platform Cable
USB, using the SPI programming mode in impact (ise9.1). This works
fine.

One of these boards is at a remote site and they happen to have an old
parallel cable III available.

Does anyone know if it is possible to program a 3V3 SPI FLASH (M25P16)
using the parallel cable III? Do I need a specific impact version for
this or can I just use the 9.1 or the latest version?


This should work. I program 3.3 V CPLDs here with no problem using a
parallel cable III. I am now mostly using iSE 10.1 and it seems to work
fine.

OK, thanks. Hope we can try it early next week.

In the mean time I have found the parallel cable III schematic. It's so
simple, I'm tempted to build it just for testing the above. In fact, it
looks very familiar, a bit like the jtag wiggler interface. Must have one
somewhere lying around. Hmm, just googled it, it's a bit different.

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

Yow! It's a hole all the way to downtown Burbank!

 

[Jon Elson]

On 03/02/2011 04:26 PM, Stef wrote:

In the mean time I have found the parallel cable III schematic. It's so
simple, I'm tempted to build it just for testing the above. In fact, it
looks very familiar, a bit like the jtag wiggler interface. Must have one
somewhere lying around. Hmm, just googled it, it's a bit different.

Yes, I have repaired our several times when ESD or whatever popped the
one chip in there. Just a voltage level translator and buffer.

Jon

 

[Stef]

In comp.arch.fpga,
Jon Elson <jmelson@wustl.edu> wrote:

On 03/02/2011 04:26 PM, Stef wrote:


In the mean time I have found the parallel cable III schematic. It's so
simple, I'm tempted to build it just for testing the above. In fact, it
looks very familiar, a bit like the jtag wiggler interface. Must have one
somewhere lying around. Hmm, just googled it, it's a bit different.


Yes, I have repaired our several times when ESD or whatever popped the
one chip in there. Just a voltage level translator and buffer.

Level translator? Are you sure have the parallel cable III? The schematic
I got from the Xilinx website only uses 2 pieces of 74HC125 buffers, no
translators. Only translation I see is some series resistors and probably
the assumption that dropping 3V3 two times over a 1N5817 is just enough
to get a high at the printer port.


--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

The turtle lives 'twixt plated decks
Which practically conceal its sex.
I think it clever of the turtle
In such a fix to be so fertile.
-- Ogden Nash

 

[Jon Elson]

On 03/03/2011 05:27 PM, Stef wrote:

Level translator? Are you sure have the parallel cable III? The schematic
I got from the Xilinx website only uses 2 pieces of 74HC125 buffers, no
translators. Only translation I see is some series resistors and probably
the assumption that dropping 3V3 two times over a 1N5817 is just enough
to get a high at the printer port.

Yes, they use the HC125 plus some passives as a really cheap level
translator that is pretty insensitive to odd power supply voltages.

Jon

 

[Stef]

In comp.arch.fpga,
Jon Elson <jmelson@wustl.edu> wrote:

On 03/03/2011 05:27 PM, Stef wrote:

Level translator? Are you sure have the parallel cable III? The schematic
I got from the Xilinx website only uses 2 pieces of 74HC125 buffers, no
translators. Only translation I see is some series resistors and probably
the assumption that dropping 3V3 two times over a 1N5817 is just enough
to get a high at the printer port.


Yes, they use the HC125 plus some passives as a really cheap level
translator that is pretty insensitive to odd power supply voltages.

Ah, got the impression you meant an explicit translator chip. But
indeed the function of the circuit is some level conversion.

Just tried an even simpler version with resistors only (had no 74HC125
and 1N5817 available). That sort of worked, I was able to read the
device ID and erase it. Programming seemed to go OK, but verify failed.
Reading back the device and looking at the hex file showed most bytes
where programmed OK.

In fact, I got some simular behaviour using the platform cable USB. So
the malfunction may not even be entirely atributed to the cheap-ass
cable III imitation. ;-)

So cable III (a proper one or good imitation) seems perfectly OK for
the required job. Thanks for the input.

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

You know what they say -- the sweetest word in the English language is revenge.
-- Peter Beard