Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG

R

rider

Guest
Hi!

I am using a Spartan 2 XC2S150 Xilinx FPGA. I have a few questions on
the Parallel Cable 4 used for the configuration:

1)The PC4 has a pin "Vref". If i am using Spartan 2 XC2S150 with
Vcco=3.3V and VCCINT=2.5, what should i connect to Vref? 3.3 or 2.5?

2)The new Xilinx Platform PROMS can be In System Programmed via JTAG.
They show a configuration diagram in which the TMS,TCK,TDI pins from
the JTAG connector are connected to the PROMS TMS,TCK and TDI pins.
The TDO pin of PROM is connecte dto FPGAs TDI pin, and finally FPGAs
TDO pin connected to JTAG connector's TDO pin. The TMS and TCK pins
from the connector are also connected to FPGAs TMS and TCK pins. In
addition to this, the FPGA and PROM are shown connecte din Master
Serial mode. Please See page 8 fig: 5 of :

http://direct.xilinx.com/bvdocs/publications/ds123.pdf

The question is that why is the diagram involving "FPGA" into JTAG
signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the fact that
FPGA can be configured by Master Serial mode after PROM is configued
through JTAG. ? Can this setup also configure FPGA directly through
JTAG? or its just for Boundary scan of the FPGA?

Please help. Thanks

Rider
 
shabana_rizvi@yahoo.com (rider) wrote in message news:<ca3a68c8.0309190250.7c39fb72@posting.google.com>...
Hi!

I am using a Spartan 2 XC2S150 Xilinx FPGA. I have a few questions on
the Parallel Cable 4 used for the configuration:

1)The PC4 has a pin "Vref". If i am using Spartan 2 XC2S150 with
Vcco=3.3V and VCCINT=2.5, what should i connect to Vref? 3.3 or 2.5?
Click to expand...
3.3V (2.5 would possible also work, but not correct)

2)The new Xilinx Platform PROMS can be In System Programmed via JTAG.
They show a configuration diagram in which the TMS,TCK,TDI pins from
the JTAG connector are connected to the PROMS TMS,TCK and TDI pins.
The TDO pin of PROM is connecte dto FPGAs TDI pin, and finally FPGAs
TDO pin connected to JTAG connector's TDO pin. The TMS and TCK pins
from the connector are also connected to FPGAs TMS and TCK pins. In
addition to this, the FPGA and PROM are shown connecte din Master
Serial mode. Please See page 8 fig: 5 of :

http://direct.xilinx.com/bvdocs/publications/ds123.pdf

The question is that why is the diagram involving "FPGA" into JTAG
signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the fact that
FPGA can be configured by Master Serial mode after PROM is configued
through JTAG. ? Can this setup also configure FPGA directly through
JTAG? or its just for Boundary scan of the FPGA?
Click to expand...
you are right, if you dont want to download the FPGA over JTAG
and dont want todo boundary scan (boundary scan is not supported
by Cable IV anyway) you can leave the FPGA JTAG pins unconnected.

antti
 
Antti Lukats wrote:

shabana_rizvi@yahoo.com (rider) wrote in message news:<ca3a68c8.0309190250.7c39fb72@posting.google.com>...
Hi!

I am using a Spartan 2 XC2S150 Xilinx FPGA. I have a few questions on
the Parallel Cable 4 used for the configuration:

1)The PC4 has a pin "Vref". If i am using Spartan 2 XC2S150 with
Vcco=3.3V and VCCINT=2.5, what should i connect to Vref? 3.3 or 2.5?

3.3V (2.5 would possible also work, but not correct)

2)The new Xilinx Platform PROMS can be In System Programmed via JTAG.
They show a configuration diagram in which the TMS,TCK,TDI pins from
the JTAG connector are connected to the PROMS TMS,TCK and TDI pins.
The TDO pin of PROM is connecte dto FPGAs TDI pin, and finally FPGAs
TDO pin connected to JTAG connector's TDO pin. The TMS and TCK pins
from the connector are also connected to FPGAs TMS and TCK pins. In
addition to this, the FPGA and PROM are shown connecte din Master
Serial mode. Please See page 8 fig: 5 of :

http://direct.xilinx.com/bvdocs/publications/ds123.pdf

The question is that why is the diagram involving "FPGA" into JTAG
signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the fact that
FPGA can be configured by Master Serial mode after PROM is configued
through JTAG. ? Can this setup also configure FPGA directly through
JTAG? or its just for Boundary scan of the FPGA?

you are right, if you dont want to download the FPGA over JTAG
and dont want todo boundary scan (boundary scan is not supported
by Cable IV anyway)
Click to expand...
Antti,
why are you saying that the boundary scan is not supported with PAR cable IV ?? - or it's a wild guess...

Aurash

you can leave the FPGA JTAG pins unconnected.

antti
Click to expand...
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324
 
"rider" <shabana_rizvi@yahoo.com> ha scritto nel messaggio
news:ca3a68c8.0309190250.7c39fb72@posting.google.com...

The question is that why is the diagram involving "FPGA"
into JTAG
signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the
fact that
FPGA can be configured by Master Serial mode after PROM is
configued
through JTAG. ? Can this setup also configure FPGA
directly through
JTAG? or its just for Boundary scan of the FPGA?
Click to expand...
Yes, you can also configure the FPGA directly via JTAG (it can be useful
for debug: programming a FLASH PROM takes at least 20-30 seconds), but
obviously when you power off, the configuration is lost.

If you compile a bitfile with CCLK as starting clock and try to load it
via JTAG, iMPACT outputs a warning and (if you want) it also changes on
the fly the startup clock to JTAG. This is useful if you want to use the
same bitfile either for PROM and FPGA (no need to recompile).

You can also connect only the FLASH PROM to JTAG, leaving unconnected
the FPGA; actually, in a Xilinx application note for an earlier
configuration PROM they suggested to connect the configuration PROMs and
the FPGAs to two different JTAG chains (I don't remember the exact
reason, it had to do with some reliability considerations).

--
Lorenzo
 
Aurelian Lazarut <aurash@xilinx.com> wrote in message news:<3F6B1811.FD334DE@xilinx.com>...
Antti Lukats wrote:

Antti,
why are you saying that the boundary scan is not supported with PAR cable
IV ?? - or it's a wild guess...
Aurash
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324
Click to expand...
Dear Xilinx Verification Engineer,

No it is not a wild guess. Sure Cable IV hardware support all JTAG
(inclusive boundary scan of course) but 99% of Xilinx customers who
own Cable IV can not use it for boundary scan because there are no
software available for that purpose.

Cable IV:
hardware is boundary scan capable
can not be used for boundary scan because no software or API is available.

I had a pretty urgent need to use boundary during development of on board
with Xilinx FPGA, I have Cable IV (only because it was bundled with
ML300 kit), but I could not use Cable IV, because the lack of software.

Cable IV hardware description and software driver API are all kept Xilinx
confidential and secret, so 3rd party software can not use Cable IV.

If the API (or register level description of the hardware interface)
would be public it would be real simple to modify STAPL player to support
Cable IV. Unfortunatly this is not possible and STAPL player hardware support
ends with Cable III (i.e. simple LPT download cable).
Xilinx provided XSVF player also does not support Cable IV.


There is only one wacked way to use Cable IV for boundary scan, but that
really not an option - SystemACE files may contain SVF so if you have systemACE
that you program using Cable IV then you could optionally create a SVF that
does the needed boundary scan, program the systemACE and let systemACE to
perform the JTAG boundary scan.

Except that I am not aware of any means of using Cable IV for boundary scan.
Correct me if I am wrong. There might be some JTAG software that cost some
thousands of $$$ and support Cable IV, but an regular Xilinx customer who
has to deal with Xilinx FPGAs and owns Cable IV can not use it boundary scan.

PLEASE, PLEASE SAY I am wrong. (I dont think I am)

antti
who does not work for xilinx but in most cases knows more than those who do.
 
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<bkpv3j$1f51@cliff.xsj.xilinx.com>...
Antti,
[snip]
- Thanks for your suggestions in this e-mail thread. Please don't
hesitate to open a case with the Xilinx hotline for other additional
suggestions that you have for iMPACT to make it a more user-friendly tool.

Regards, Wei
Xilinx Applications
Click to expand...
one word XHWIF
two words iMpact + XHWIF

in other words publish some (any) API to talk to Cable IV (and all upcoming
new cables) it could be xilinx XHWIF API, could be something else.
but some API should be available.

thats it. dont see a point opening a webcase on that?
or dont see xilinx could close the webcase :)

antti
PS 6.1 is released, but it looks that Foundation 5.2 users can not
upgrade what is a realy pity :(
as is pity that Chipscope 5.1 users cant upgrade to Chipscope 5.2
(small things you dont know until you buy xilinx software)
 
Antti,

iMPACT does allow user to download, verify, get device ID via JTAG. For
other functions such as EXTEST, INTEST, etc, you can shift in such
instructions with iMPACT's Debug Chain functionality. This feature
allows you to move through the 16 TAP controller states and shift in TDI
data.

With 6.1i iMPACT you'll be able to genrate and program the Xilinx part
with SVF (via inbuild XSVF player function).

If iMPACT isn't detecting the Parallel Cable for you, please see Xilinx
solution 15742 for debugging tips and contact the Xilinx hotline support
for further issues.

Regards, Wei
Xilinx Applications

Antti Lukats wrote:

Aurelian Lazarut <aurash@xilinx.com> wrote in message news:<3F6B1811.FD334DE@xilinx.com>...

Antti Lukats wrote:

Antti,
why are you saying that the boundary scan is not supported with PAR cable
IV ?? - or it's a wild guess...
Aurash
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324


Dear Xilinx Verification Engineer,

No it is not a wild guess. Sure Cable IV hardware support all JTAG
(inclusive boundary scan of course) but 99% of Xilinx customers who
own Cable IV can not use it for boundary scan because there are no
software available for that purpose.

Cable IV:
hardware is boundary scan capable
can not be used for boundary scan because no software or API is available.

I had a pretty urgent need to use boundary during development of on board
with Xilinx FPGA, I have Cable IV (only because it was bundled with
ML300 kit), but I could not use Cable IV, because the lack of software.

Cable IV hardware description and software driver API are all kept Xilinx
confidential and secret, so 3rd party software can not use Cable IV.

If the API (or register level description of the hardware interface)
would be public it would be real simple to modify STAPL player to support
Cable IV. Unfortunatly this is not possible and STAPL player hardware support
ends with Cable III (i.e. simple LPT download cable).
Xilinx provided XSVF player also does not support Cable IV.


There is only one wacked way to use Cable IV for boundary scan, but that
really not an option - SystemACE files may contain SVF so if you have systemACE
that you program using Cable IV then you could optionally create a SVF that
does the needed boundary scan, program the systemACE and let systemACE to
perform the JTAG boundary scan.

Except that I am not aware of any means of using Cable IV for boundary scan.
Correct me if I am wrong. There might be some JTAG software that cost some
thousands of $$$ and support Cable IV, but an regular Xilinx customer who
has to deal with Xilinx FPGAs and owns Cable IV can not use it boundary scan.

PLEASE, PLEASE SAY I am wrong. (I dont think I am)

antti
who does not work for xilinx but in most cases knows more than those who do.
Click to expand...
 
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<bkn59c$ki52@cliff.xsj.xilinx.com>...
Antti,

iMPACT does allow user to download, verify, get device ID via JTAG. For
other functions such as EXTEST, INTEST, etc, you can shift in such
instructions with iMPACT's Debug Chain functionality. This feature
allows you to move through the 16 TAP controller states and shift in TDI
data.

With 6.1i iMPACT you'll be able to genrate and program the Xilinx part
with SVF (via inbuild XSVF player function).

If iMPACT isn't detecting the Parallel Cable for you, please see Xilinx
solution 15742 for debugging tips and contact the Xilinx hotline support
for further issues.

Regards, Wei
Xilinx Applications

Antti Lukats wrote:
Click to expand...
Dear Xilinx Applications!

thank you for the answer, but it is no anser actually, - see
using ISE 5.2, if I want to play a STAPL file that programs a 2MB
Flash connected to a Xilinx FPGA how do I do it with Cable IV?
Answer is I CAN NOT.

With Cable III there there are no problems, I just execute the STAPL
with a STAPL player and its all done.

Your answer about using 'Debug Chain Functionality' is really really stupid!
As far as I can see it is only possible todo it in iteractive mode.
To programa 2MB flash, it takes maybe over 10,000,000,000 transactions
on JTAG port (depends on chain lenght) if I do it manually by clicking
on buttons in iMpact - ridiculuous.


if new iMpact allows SVF playback its a little bit help, but iMpact
is really really a nighmare (as others on this list have said also)

thanks for your time (well, you get paid for it)

antti lukats
PS my statement stays: Cable IV is not useable for Boundary Scan.

PPS if you now say I a stupid and should read iMpact manual, then
FYI I am not and I just did:

"bsdebug [-start] [-reset] [-stop] [-tms 0|1] [-tdi
0|1] [-tck <number>] [-loop <number>] :Executes the

Boundary-Scan Debug instruction which shifts in the instruction
and data values specified by -tms and -tdi."


There is no way to capture TDO !!!!!
what means the debug chain batch command can not be used for boundary scan.
 
Antti,

Let me try to summarize the points here.

-Yes, parallel cable IV is only supported by iMPACT to program all
Xilinx parts. It has bypass function for 3rd party support. It supports
BSCAN operation for Xilinx parts via iMPACT.
- There are currently no plans to support playing STAPL files in iMPACT
- The Debug Chain GUI functionality was enhanced for 6.1i iMPACT to
provide TDO capture ability during DR-SCAN and IR-SCAN functions. The
TAP state machine is also provided in the GUI as a reference.
The Debug Chain feature was included for simple chain debugging, and
device debugging using the capture-IR bits read back on TDO.

Example iMPACT log:
// *** BATCH CMD : bsdebug -start
// *** BATCH CMD : bsdebug -tms 1 -tdi 1 -tck 5
TDO Capture Data: 0
// *** BATCH CMD : bsdebug -scanir 11111111
TDO Capture Data: 00000001
// *** BATCH CMD : bsdebug -scanir 11111110
TDO Capture Data: 00000001
// *** BATCH CMD : bsdebug -scandr 11111111111111111111111111111111
TDO Capture Data: 00000101000000100110000010010011

-Yes, Debug chain function would not be effective to program a part.
Third Party Boundary Scan Tools, Automatic Test Equipment (ATE) Tools,
or Embedded Solutions are the alternatives for programming Xilinx
devices along with third party devices. I'm sure you know a lot more
about this.
http://www.support.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?title=isp_3ptytools_page

http://www.support.xilinx.com/xlnx/xil_prodcat_product.jsp?title=isp_ate_page

- Thanks for your suggestions in this e-mail thread. Please don't
hesitate to open a case with the Xilinx hotline for other additional
suggestions that you have for iMPACT to make it a more user-friendly tool.

Regards, Wei
Xilinx Applications

Antti Lukats wrote:
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<bkn59c$ki52@cliff.xsj.xilinx.com>...

Antti,

iMPACT does allow user to download, verify, get device ID via JTAG. For
other functions such as EXTEST, INTEST, etc, you can shift in such
instructions with iMPACT's Debug Chain functionality. This feature
allows you to move through the 16 TAP controller states and shift in TDI
data.

With 6.1i iMPACT you'll be able to genrate and program the Xilinx part
with SVF (via inbuild XSVF player function).

If iMPACT isn't detecting the Parallel Cable for you, please see Xilinx
solution 15742 for debugging tips and contact the Xilinx hotline support
for further issues.

Regards, Wei
Xilinx Applications

Antti Lukats wrote:


Dear Xilinx Applications!

thank you for the answer, but it is no anser actually, - see
using ISE 5.2, if I want to play a STAPL file that programs a 2MB
Flash connected to a Xilinx FPGA how do I do it with Cable IV?
Answer is I CAN NOT.

With Cable III there there are no problems, I just execute the STAPL
with a STAPL player and its all done.

Your answer about using 'Debug Chain Functionality' is really really stupid!
As far as I can see it is only possible todo it in iteractive mode.
To programa 2MB flash, it takes maybe over 10,000,000,000 transactions
on JTAG port (depends on chain lenght) if I do it manually by clicking
on buttons in iMpact - ridiculuous.


if new iMpact allows SVF playback its a little bit help, but iMpact
is really really a nighmare (as others on this list have said also)

thanks for your time (well, you get paid for it)

antti lukats
PS my statement stays: Cable IV is not useable for Boundary Scan.

PPS if you now say I a stupid and should read iMpact manual, then
FYI I am not and I just did:

"bsdebug [-start] [-reset] [-stop] [-tms 0|1] [-tdi
0|1] [-tck <number>] [-loop <number>] :Executes the

Boundary-Scan Debug instruction which shifts in the instruction
and data values specified by -tms and -tdi."


There is no way to capture TDO !!!!!
what means the debug chain batch command can not be used for boundary scan.
Click to expand...
 
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