Xilinx PAR guide files

[Brannon King]

I've posted below a cut from my .par file. I'm attempting to use an "exact"
guide file. You'll note it has about 25% of the nets fall under "Rejected
Implicit/Internal." This seems to be a trend; can someone explain that to
me? Perhaps you could explain this report in general? (i.e., why it lists
things twice, why it was unable to route all the signals that had the names
matching, etc.)


Xilinx Place and Route Guide Results File
=========================================

Guide Summary Report:

Design Totals:
Components:
Name matched: 2363 out of 2964 79%
Total guided: 2363 out of 2363 100%

Signals:
Rejected Implicit/Internal: 2046 out of 8166
LOGIC0/LOGIC1 nets ignored: 2 out of 6120
Name matched: 6118 out of 6118 100%
Total guided: 3331 out of 6118 54%
Total connections guided: 12000



Guide file: ".\last\HWHW_Elements_C_PEn_RPEn_R_R.ncd" Guide mode:
"exact"

Components:
Name matched: 2363 out of 2964 79%
Total guided: 2363 out of 2363 100%

Signals:
LOGIC0/LOGIC1 nets ignored: 2 out of 8166
Name matched: 6118 out of 8164 74%
Total guided: 3331 out of 6118 54%
Total connections guided: 12000


For a detailed guide report refer to the "HWHW_Elements_C_PEn_RPEn_R_R.grf"

file.

Device utilization summary:

Number of External IOBs 96 out of 824 11%
Number of LOCed External IOBs 96 out of 96 100%

Number of RAMB16s 4 out of 144 2%
Number of SLICEs 2858 out of 33792 8%

Number of BUFGMUXs 5 out of 16 31%
Number of DCMs 1 out of 12 8%

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