Xilinx multiplier core instantiation for Virtex4

[D Stanford]

I'm running into some unexpectedly big problems instantiating some
multiplier cores for a Virtex4 part. I'm porting a design originally
in a Virtex2 part over to a Virtex4, and everything has run smoothly
except the multiplier cores. I haven't had problems with FIFO cores or
dualport RAM cores or ROMs, but the multipliers seem to cause a ton of
problems.

For the Virtex4, we're using XST in ISE 8.2 for synthesis. The first
problem was that mapping failed with an unexpected (ie unexplained)
error. It took a while to isolate this to the VHDL files with the
multiplier cores in them. So I regenerated the cores, using the Xilinx
CoreGen tool.

Still no luck. Now, the translator complains that the multiplier name
called out in the EDN file doesn't exist.

So I've switched to trying to instantiate them direclty, as the
CoreGen documentation says is possible. Now the HDL compiler won't
recognize mult_gen_v9_0 as a valid entity, even though the multiplier
core documentation says that it should.

So I have a couple questions from my experience

1) Am I correct in presuming that the Virtex2 multiplier cores won't
work with a Virtex4 part?

2) Is there any generic advice (or more detail I can provide) on
creating cores for XST synthesis using CoreGen?

3) Is there any advice (or more detail I can provide) on directly
instantiating the mult_gen_v9_0?

 

[Duane Clark]

D Stanford wrote:

I'm running into some unexpectedly big problems instantiating some
multiplier cores for a Virtex4 part. I'm porting a design originally
in a Virtex2 part over to a Virtex4, and everything has run smoothly
except the multiplier cores. I haven't had problems with FIFO cores or
dualport RAM cores or ROMs, but the multipliers seem to cause a ton of
problems.

Why not just infer the multipliers? In the past that may have been a
problem, but XST will now infer them just fine.
M <= X * Y; -- should be all that you need

 

[D Stanford]

On Mar 23, 2:54 pm, Duane Clark <junkm...@junkmail.com> wrote:

D Stanford wrote:
I'm running into some unexpectedly big problems instantiating some
multiplier cores for a Virtex4 part. I'm porting a design originally
in a Virtex2 part over to a Virtex4, and everything has run smoothly
except the multiplier cores. I haven't had problems with FIFO cores or
dualport RAM cores or ROMs, but the multipliers seem to cause a ton of
problems.

Why not just infer the multipliers? In the past that may have been a
problem, but XST will now infer them just fine.
M <= X * Y; -- should be all that you need

That's the next plan (plan D at this point).

 

[JK]

I also got similar kind of problems.
For these cores have u added xco files or vhd file generated by xco
files?
I added xco file to project instead of vhd file, n problem got solved.
U can try both options...

Regards,
JK

 

[D Stanford]

On Mar 24, 6:49 pm, "JK" <krishna.januman...@gmail.com> wrote:

I also got similar kind of problems.
For these cores have u added xco files or vhd file generated by xco
files?
I added xco file to project instead of vhd file, n problem got solved.
U can try both options...

Regards,
JK

That's really surprising to me. The .xco is the coregen project file.
When you add it to your Xilinx ISE project it gives you good results
with the multiplier cores?

 

[JK]

On Mar 26, 7:33 pm, "D Stanford" <David.Stanf...@gmail.com> wrote:

On Mar 24, 6:49 pm, "JK" <krishna.januman...@gmail.com> wrote:

I also got similar kind of problems.
For these cores have u added xco files or vhd file generated by xco
files?
I added xco file to project instead of vhd file, n problem got solved.
U can try both options...

Regards,
JK

That's really surprising to me. The .xco is the coregen project file.
When you add it to your Xilinx ISE project it gives you good results
with the multiplier cores?

I tried all the options when this multiplier core vhd file was giving
errors.
When you work with Xilinx software, sometimes you need to work without
applying mind... hahahaha
Honestly, I haven't gone through this problem deeply, as adding xco
file to project cleared all errors.

Regards,
JK

 

[self]

JK wrote:

On Mar 26, 7:33 pm, "D Stanford" <David.Stanf...@gmail.com> wrote:
On Mar 24, 6:49 pm, "JK" <krishna.januman...@gmail.com> wrote:

I also got similar kind of problems.
For these cores have u added xco files or vhd file generated by xco
files?
I added xco file to project instead of vhd file, n problem got solved.
U can try both options...
Regards,
JK
That's really surprising to me. The .xco is the coregen project file.
When you add it to your Xilinx ISE project it gives you good results
with the multiplier cores?

I tried all the options when this multiplier core vhd file was giving
errors.
When you work with Xilinx software, sometimes you need to work without
applying mind... hahahaha
Honestly, I haven't gone through this problem deeply, as adding xco
file to project cleared all errors.

Regards,
JK

The .xco file is not the coregen project file it is just the definition

file for the single core. Generally it is the .xco file you want to
include in your project for implementation. The .vhd that comes out of
coregen is just for simulation.

If you don't want to include the .xco file in your project you can just
add it's path to the "macro search path". Map will then find the .ngc
netlist at map time.

In any case, do not include the coregen .vhd output because that is not
synthesizable code.

Pete