Xilinx - Multi Volt Interfacing

L

Lockie

Guest
Hey All,

Im using a XC2S300E and a 5V CPU. The XC2S300E implements a simple memory
interface to the CPU.

My question is related to using the 5V CPU with the 3.3V XC2S I/O Pins. In
a past design i've used a XC95288 (CPLD), and had to use strong pull up
resistors (<1K to 5V) to meet the timing requirements of the bus, along with
floating the Xilinx I/O Pins to implement a bi-directional interface.

In this new design its not suitable to use such a "dodgey" method of
interfacing.

Can anyone suggest any possible solutions I could try?

Thanks in advance.
Lockie.
 
Hello Lockie,

I donot know your previous implementation was on XC95288 or the XC95288XL
family, the thing here is the XL devices have 5V tolerant i/o, and you can
interface them straight to the FPGA i/o. Pull up is required in case of 5V
CMOS only.
But in the case of Spartan2E, the i/o's are not 5V tolerant, and thus you
cannot directly interface it to a 5V device. You need to have a series
resistor or a buffer in between. In your case as you want to interface the
fpga to the cpu, which in your case I presume to be 5V CMOS you can only use
a level translator or bidirectional buffer for e.g. from IDT, www.idt.com.
If you don't want to use external buffer and use the pull up resistor
arrangement, you will need to use the Spartan2 family instead, which has 5V
tolerant I/o.

Regards
Sandeep
"Lockie" <biglockie@hotmail.com> wrote in message
news:3fa5fdfc@dnews.tpgi.com.au...
Hey All,

Im using a XC2S300E and a 5V CPU. The XC2S300E implements a simple memory
interface to the CPU.

My question is related to using the 5V CPU with the 3.3V XC2S I/O Pins.
In
a past design i've used a XC95288 (CPLD), and had to use strong pull up
resistors (<1K to 5V) to meet the timing requirements of the bus, along
with
floating the Xilinx I/O Pins to implement a bi-directional interface.

In this new design its not suitable to use such a "dodgey" method of
interfacing.

Can anyone suggest any possible solutions I could try?

Thanks in advance.
Lockie.
Click to expand...
 
Sandeep,
Thanks for your information,

Firstly i forgot to mention the device is a XC95288XL, and my reason for not
wanting to use a strong pull-up resistor was the amount of heating caused to
the device. (which im advised is well within tollerance).

Secondly, i seem to have some conflicting information with relation to the
5V issue. I received a link to the virtex information on Xilinx's web site,
this makes mention of the device driving a 5V Load, and accepting a 5V
input, but not in both directions.
It is unfortunate but most of the devices in my system are 5V and require
bi-directional support (CPU, LCD Panel, RTC, etc).
I use about 120 of the I/O's for 5V interfacing, and if i use a 1K pull up
resistor (so as i can still meet timing requirements), i find myself using
600mA+ of current just for the I.O's. I know that each pin is rated to
10mA, which is what i base my calc's on, but don't you think that seems a
little excessive.??

Im looking now into the interfacing devices,
Once again , thanks for you help.
Lockie.


"Sandeep Kulkarni" <sandeep@insight.memec.co.in> wrote in message
news:bo75gf$17dhsb$1@ID-199516.news.uni-berlin.de...
Hello Lockie,

I donot know your previous implementation was on XC95288 or the XC95288XL
family, the thing here is the XL devices have 5V tolerant i/o, and you can
interface them straight to the FPGA i/o. Pull up is required in case of 5V
CMOS only.
But in the case of Spartan2E, the i/o's are not 5V tolerant, and thus you
cannot directly interface it to a 5V device. You need to have a series
resistor or a buffer in between. In your case as you want to interface the
fpga to the cpu, which in your case I presume to be 5V CMOS you can only
use
a level translator or bidirectional buffer for e.g. from IDT, www.idt.com.
If you don't want to use external buffer and use the pull up resistor
arrangement, you will need to use the Spartan2 family instead, which has
5V
tolerant I/o.

Regards
Sandeep
"Lockie" <biglockie@hotmail.com> wrote in message
news:3fa5fdfc@dnews.tpgi.com.au...
Hey All,

Im using a XC2S300E and a 5V CPU. The XC2S300E implements a simple
memory
interface to the CPU.

My question is related to using the 5V CPU with the 3.3V XC2S I/O Pins.
In
a past design i've used a XC95288 (CPLD), and had to use strong pull up
resistors (<1K to 5V) to meet the timing requirements of the bus, along
with
floating the Xilinx I/O Pins to implement a bi-directional interface.

In this new design its not suitable to use such a "dodgey" method of
interfacing.

Can anyone suggest any possible solutions I could try?

Thanks in advance.
Lockie.
Click to expand...
 
Lockie <biglockie@hotmail.com> wrote in message
news:3fa78ae6@dnews.tpgi.com.au...
Sandeep,
Thanks for your information,

Firstly i forgot to mention the device is a XC95288XL, and my reason for
not
wanting to use a strong pull-up resistor was the amount of heating caused
to
the device. (which im advised is well within tollerance).

Secondly, i seem to have some conflicting information with relation to the
5V issue. I received a link to the virtex information on Xilinx's web
site,
this makes mention of the device driving a 5V Load, and accepting a 5V
input, but not in both directions.
It is unfortunate but most of the devices in my system are 5V and require
bi-directional support (CPU, LCD Panel, RTC, etc).
I use about 120 of the I/O's for 5V interfacing, and if i use a 1K pull up
resistor (so as i can still meet timing requirements), i find myself using
600mA+ of current just for the I.O's. I know that each pin is rated to
10mA, which is what i base my calc's on, but don't you think that seems a
little excessive.??
Im looking now into the interfacing devices,
Once again , thanks for you help.
Lockie.
Click to expand...
What are the Vih levels of your 5V devices?

If they are all < 3V you could probably use IDT's quickswitch devices.
These are bidirectional voltage clamps which will restrict the
voltage to your FPGA dependant on the bias level on the control
pins.

There's an app note, AN11 from memory, on the IDT site which explains
their use.

Hope this helps,

Nial Stewart


------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk
 
Regarding 95288XL:

Input:
The pins are 5-V tolerant, so you can drive a full-swing 5 V signal into
the input.

Output:
When used as an output, it obviously only drives up to the 3.3 V rail.
If your 5-V device uses "TTL" thresholds, it only requires a Vih of 2.4
V, so there is no problem. If your 5-V device has "CMOS" thresholds, you
need a pull-up resistor, and you also need to 3-state the CPLD outputs
(otherwise the pull-up transistor will conduct current backwards and
clamp the pin to Vcc anyhow.)

You may want to read about a circuit trick that speeds up the pull-up,
and has been very successful in FPGAs. This is from TechXclusives "Six
Easy Pieces" on the Xilinx website, where you also find the simple
schematic :

" 5. Driving a 5V Signal from a 3.3V Output

When a CMOS-level 5V input is driven, the output High voltage from a
3.3V device is marginal. If the 3.3V output is 5V tolerant, a pull-up
resistor to 5V can pull the output that is in a 3-state condition all
the way to 5V. The problem is the slow rise time of tens or hundreds of
nanoseconds, which is caused by the capacitive load. This circuit
greatly reduces the rise time by keeping the active pull-up engaged
until the output voltage has passed the threshold voltage of ~1.6V.
Slowing down the internal input signal and 2-input AND gate will speed
up the rise time even more. "

I have never implemented this in a CPLD, but it might work there also.

Peter Alfke

 
Thanks for all the support guys,

Ive carefully studied the threshold voltages of my various 5V devices and
found the margins too small for driving with 3.3V.

I am forced to use 74LVX4245 / 74LVX3245 devices for interfacing. Although
its extra components on the board, i'd feel safer using the translators,
especially when the design matures and we can move towards greater speed
increases using clock multiplication, etc.

Thanks for all the suggestions.
Lockie.


"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FA7E9E3.F9DD1AF0@xilinx.com...
Regarding 95288XL:

Input:
The pins are 5-V tolerant, so you can drive a full-swing 5 V signal into
the input.

Output:
When used as an output, it obviously only drives up to the 3.3 V rail.
If your 5-V device uses "TTL" thresholds, it only requires a Vih of 2.4
V, so there is no problem. If your 5-V device has "CMOS" thresholds, you
need a pull-up resistor, and you also need to 3-state the CPLD outputs
(otherwise the pull-up transistor will conduct current backwards and
clamp the pin to Vcc anyhow.)

You may want to read about a circuit trick that speeds up the pull-up,
and has been very successful in FPGAs. This is from TechXclusives "Six
Easy Pieces" on the Xilinx website, where you also find the simple
schematic :

" 5. Driving a 5V Signal from a 3.3V Output

When a CMOS-level 5V input is driven, the output High voltage from a
3.3V device is marginal. If the 3.3V output is 5V tolerant, a pull-up
resistor to 5V can pull the output that is in a 3-state condition all
the way to 5V. The problem is the slow rise time of tens or hundreds of
nanoseconds, which is caused by the capacitive load. This circuit
greatly reduces the rise time by keeping the active pull-up engaged
until the output voltage has passed the threshold voltage of ~1.6V.
Slowing down the internal input signal and 2-input AND gate will speed
up the rise time even more. "

I have never implemented this in a CPLD, but it might work there also.

Peter Alfke
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top