Xilinx Modelsim XE-III 6.2g no more Systemverilog support?

[Xilinx User]

I upgraded my Modelsim XE-III 6.2c starter edition to
Modelsm XE-III 6.2g starter edition. Before isntalling the
new software, I uninstalled 6.2c (from Control Panel), and
then I deleted the
\modelsim_xe_starter directory on my hard-drive.

After the upgrade, I recycled the license.dat file from
the old modelsim starter edition. (The license checker
says it's valid.) I tried running some Systemverilog
testbenches I had... all of them produce the same
fatal error. I can compile the code without problem.
But when I try to start the simulation (using the 'vsim'
command from the Modelsim command-line), I get
the following error message:

\modelsiim_xe_starter\win32xeoem/../sv_std is not compiled with XE
simulator.

My Systemverilog testbenches have a combination
of Verilog-2001 and Systemverilog modules, but I
tried a simple testcase with just a single Systemverilog
module -- same problem. This was just a simple .sv file
with an interface declaration (but no 'advanced' features
that require the Questa license.) I also compiled a simple
(single-file) VHDL testbench and (single-file) Verilog-2001
testbench. Both compiled and simulated just fine.

i was going to suggest buying a few XE-III (full) licenses,
but that was contingent upon, apparently, an
undocumented/unofficial support for Systemverilog. Now,
I'll probably suggest getting (Mentor) Modelsim-PE.

Anyway, Modelsim XE-III 6.2c starter-edition ran
Systemverilog simulations just fine. So did Xilinx remove
this feature from XE-III 6.2g? Nowhere in Xilinx's
online documentation, does Xilinx claim to support
Systemverilog. But I'd like to get a definitive/official
answer.

 

[HT-Lab]

"Xilinx User" <anonymous@net.com> wrote in message
news:h1Dgi.4487$vi5.1602@newssvr17.news.prodigy.net...
snip

i was going to suggest buying a few XE-III (full) licenses,
but that was contingent upon, apparently, an
undocumented/unofficial support for Systemverilog. Now,
I'll probably suggest getting (Mentor) Modelsim-PE.

Anyway, Modelsim XE-III 6.2c starter-edition ran
Systemverilog simulations just fine. So did Xilinx remove
this feature from XE-III 6.2g? Nowhere in Xilinx's
online documentation, does Xilinx claim to support
Systemverilog. But I'd like to get a definitive/official
answer.

If this is indeed the case then I believe Mentor has changed their OEM
agreement with Xilinx since the difference has always been simulation speed
and number of instances.

This might just been an oversight on Xilinx's part?

Do you have the sv_std folder in your installation directory? (I have it on
my PE installation).

Hans
www.ht-lab.com

 

[Xilinx User]

"HT-Lab" <hans64@ht-lab.com> wrote in message
news:x_Jgi.5846$nE2.2947@newsfe3-win.ntli.net...

Anyway, Modelsim XE-III 6.2c starter-edition ran
Systemverilog simulations just fine. So did Xilinx remove
this feature from XE-III 6.2g? Nowhere in Xilinx's
online documentation, does Xilinx claim to support
Systemverilog. But I'd like to get a definitive/official
answer.
...
Do you have the sv_std folder in your installation directory? (I have it
on my PE installation).

I checked my \modelsim_xe_starter dir, and the sv_std subdir is there.
From what I can tell, the 6.2g installer puts the files there, but the
simulator refuses to load them if the simulation contains any
Systemverilog modules/submodules.

Mentor's free Modelsim PE Student Edition (6.3p1) runs Systemverilog
simulations just fine...though I hope there isn't some kind of weird
interaction when multiple Modelsims are installed on the same
PC!

 

[Alan]

Same experience on my machine. Luckily I kept a backup of the old
Modelsim XE-III 6.2c. If you still have 6.2c laying around, you can try
this 'hack' to XE-III 6.2g:

simple copy over 6.2c's \modelsim_xe_starter\sv_std\* directory
to your new 6.2g installation.

So far, 6.2g compiles and simulates simple Systemverilog simulations,
but whether it'll crash on sims using more complex Systemverilog
syntax, who knows.

"Xilinx User" <anonymous@net.com> wrote in message
news:esOgi.7913$bP5.6493@newssvr19.news.prodigy.net...

"HT-Lab" <hans64@ht-lab.com> wrote in message
news:x_Jgi.5846$nE2.2947@newsfe3-win.ntli.net...
Anyway, Modelsim XE-III 6.2c starter-edition ran
Systemverilog simulations just fine. So did Xilinx remove
this feature from XE-III 6.2g? Nowhere in Xilinx's
online documentation, does Xilinx claim to support
Systemverilog. But I'd like to get a definitive/official
answer.
...
Do you have the sv_std folder in your installation directory? (I have it
on my PE installation).

I checked my \modelsim_xe_starter dir, and the sv_std subdir is there.
From what I can tell, the 6.2g installer puts the files there, but the
simulator refuses to load them if the simulation contains any
Systemverilog modules/submodules.

Mentor's free Modelsim PE Student Edition (6.3p1) runs Systemverilog
simulations just fine...though I hope there isn't some kind of weird
interaction when multiple Modelsims are installed on the same
PC!