Xilinx Microblaze SDRAM burst access

[Dirk Ziegelmeier]

Hello Group,

I'm currently evaluating a Xilinx Microblaze system. One of the
must-have features is a fast memcopy. Therefore, I implemented a basic
system consisting of a Microblaze core (no caches, but program runs in
BlockRAM) and a SDRAM controller. Burst support of the SDRAM core is
enabled. Burst support of the microblaze core should work
out-of-the-box according to the manuals.
The system consists of:
- Microblaze 2.0 core
- OPB bus v20
- OPB SDRAM controller

Memcopy delivers unsatisfactory performance, an analysis shows that
the main reason is that the SDRAM controller does not perform burst
accesses to the RAM. The memcopy routine is quite optimal, it consists
of four consecutive read and four write instructions, so bursting
should work in theory.

Is there anything more I need to do to get bursts to work? I already
spent two days reading manuals and FAQs trying to identify the
problem, but no success.

TIA,
Dirk

 

[steven derrien]

Hi Dirk,

Dirk Ziegelmeier wrote:

Hello Group,

[ ... ]

Memcopy delivers unsatisfactory performance, an analysis shows that
the main reason is that the SDRAM controller does not perform burst
accesses to the RAM. The memcopy routine is quite optimal, it consists
of four consecutive read and four write instructions, so bursting
should work in theory.

I might be wrong, but I doubt that the microblaze bus bridge is smart
enough to detect and organize burst directly from the cpu execution
flow. I would rather think that the burst access can only occur when you
have a cache (cache exchange data with memory line by line, and each
line transfer generates a burst).

Is there anything more I need to do to get bursts to work? I already
spent two days reading manuals and FAQs trying to identify the
problem, but no success.

TIA,
Dirk