Xilinx LVDS_25_DT termination issues????

[John Providenza]

I'm doing a high speed design with 800 MHz LVDS data input into
a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input
termination mode for the LVDS standard and looked at the
Xilinx Answer Record 17244 for further info.

It sounds like this mode may not have the issues that DCI had.

Does anyone know of any issues with using this input termination
mode?

Thanks!

John Providenza

 

[Austin Lesea]

John,

This is a true differential termination (a resistor) that is switched in
between + and - inputs.

No 'issues'.

Enjoy,

Austin

John Providenza wrote:

I'm doing a high speed design with 800 MHz LVDS data input into
a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input
termination mode for the LVDS standard and looked at the
Xilinx Answer Record 17244 for further info.

It sounds like this mode may not have the issues that DCI had.

Does anyone know of any issues with using this input termination
mode?

Thanks!

John Providenza

 

[Symon]

John,
It's working well for me so far! Beware of the requirement that the
I/O bank that uses the 'DT' input must be powered from VCCO = 2.5V.
Pain in the fecking arse if you've got lots of 3.3V I/O as well! Why
didn't Xilinx make this termination like the rest of the LVDS input
circuit and power it from VCCAUX (which is 2.5V)? Grrr. I tried a
couple of times on here to get answers about what happens when the
bank is powered from 3.3V, but didn't get very far.
Anyway, sorry about that rant, apart from that, it works on my board!
cheers, Syms.


johnp3+nospam@probo.com (John Providenza) wrote in message news:<349ef8f4.0401221405.36b58977@posting.google.com>...

I'm doing a high speed design with 800 MHz LVDS data input into
a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input
termination mode for the LVDS standard and looked at the
Xilinx Answer Record 17244 for further info.

It sounds like this mode may not have the issues that DCI had.

Does anyone know of any issues with using this input termination
mode?

Thanks!

John Providenza

 

[John Providenza]

Austin -

Thanks for the feedback. I REALLY appreciate the feedback
from you and Peter in this newsgroup.

My local FAE is nervous about using the internal DT terminating
resistors at 800 MHz input (400MHz DDR). He says he's seen
external resistors work fine at this speed, so why tempt fate?

Have you had good performance with the DT style termination at
these speeds? I'd sure like to get rid of the stubs at these
frequencies!

Thanks!

John P

Austin Lesea <austin@xilinx.com> wrote in message news:<bupm6q$8dh2@cliff.xsj.xilinx.com>...

John,

This is a true differential termination (a resistor) that is switched in
between + and - inputs.

No 'issues'.

Enjoy,

Austin

John Providenza wrote:
I'm doing a high speed design with 800 MHz LVDS data input into
a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input
termination mode for the LVDS standard and looked at the
Xilinx Answer Record 17244 for further info.

It sounds like this mode may not have the issues that DCI had.

Does anyone know of any issues with using this input termination
mode?

Thanks!

John Providenza

 

[Ray Andraka]

We looked at the DCI for an SDRAM interface. The DCI slowed down the pins too much to be useful
in that application. At 400MHz, I suspect you will find the same thing.

John Providenza wrote:

Austin -

Thanks for the feedback. I REALLY appreciate the feedback
from you and Peter in this newsgroup.

My local FAE is nervous about using the internal DT terminating
resistors at 800 MHz input (400MHz DDR). He says he's seen
external resistors work fine at this speed, so why tempt fate?

Have you had good performance with the DT style termination at
these speeds? I'd sure like to get rid of the stubs at these
frequencies!

Thanks!

John P

Austin Lesea ?austin@xilinx.com? wrote in message news:?bupm6q$8dh2@cliff.xsj.xilinx.com?...
? John,
?
? This is a true differential termination (a resistor) that is switched in
? between + and - inputs.
?
? No 'issues'.
?
? Enjoy,
?
? Austin
?
? John Providenza wrote:
? ? I'm doing a high speed design with 800 MHz LVDS data input into
? ? a Virtex2-Pro V2P7 part. I've looked at the new 'DT' input
? ? termination mode for the LVDS standard and looked at the
? ? Xilinx Answer Record 17244 for further info.
? ?
? ? It sounds like this mode may not have the issues that DCI had.
? ?
? ? Does anyone know of any issues with using this input termination
? ? mode?
? ?
? ? Thanks!
? ?
? ? John Providenza

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Brian Davis]

regarding LVDS_25_DT, John wrote:

Does anyone know of any issues with using this
input termination mode?

I recently bought a Avnet V2Pro eval board to try out
the new _DT terminators; unfortunately, as recently as
last month, they were still shipping boards with 2VP7-ES
parts, which do not support the _DT terminators or the
new DCI update modes.

If you're going to test or prototype soon, make sure
you have a part listed as supporting _DT termination in
Answer Record 17244.

The _DT terminators should address the LVDS_25_DCI
static power dissipation, DC offset, and DCI modulation
problems; however, the published differential input
buffer parasitics in the datasheet and IBIS models are
identical for both the V2Pro and the V2, so be careful
if driving the inputs from a fast LVDS/ECL device.

I'd provide some Answer Record #'s, but the Xilinx Answer
Record search function seems to be broken tonight- here's
what I recall from the last time I looked:

- the _DT terminators do not require a VRP/VRN reference
resistor pair. This suggests that they have a fixed
value, rather than being controlled by the DCI logic,
so they should be immune from any remaining DCI
modulation problems in the V2Pro

- RSDS and LVDS primitives can not co-exist in the same bank

- be careful of VCCO levels- as noted by Symon, although
the LVDS Rx's are powered by VCCAUX, the documentation
states that the banks with the _DT terminators also need
to have VCCO at 2.5V

- LVDS drivers MUST be in a 2.5V bank on the V2Pro (unlike V2)

- V2Pro DCMs do NOT support external 2X clock feedback.
This omission may affect your 800 Mbps application.

- Verify the _DT IBIS models with some simple test cases
before trusting them and your IBIS simulator.
I've had plenty of problems with differential ECL/LVDS
IBIS models and simulators in the past, and I'm not certain
IBIS 2.x can properly model differential terminators and
differential package parasitics.

Brian