Xilinx Logicore PCI64 Problem

O

owner

Guest
Hi,

I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
NGDBUILD, the design, I encounter the following errors:

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'

The error continues for the whole bus width, and for other signals as
well.
I think the ucf file specifies the constraints using "/" to reference
the instance, but the core instantiates in a different way. There is a
file by the name of "pci_lc_i.vhd" which I found the instance
PCI_AD64_IO31_OFD instantiated as:

PCI_AD64_IO31_OFD : X_FF
port map(
......

Does this mean I have to change the ucf file's constraint statements?
Can anyone in the group who has used xilinx logicore pci64 advice me
on this?

Any help is greatly appreciated.

Regards,
LC
 
I haven't used any cores released in the past year, so I'm not sure what the
*_i.* stuff is. The rest of this applies to what I learned using it a year
ago.

The core comes with several ucf and lc files associated to either "core" or
"fast". All three files will need to be included in the project. The
pcix_fast.* (for 133MHz) stuff requires the use of the *_64xf.*. Use the
pcix_core.* for all the other lc and ucf files. All the *_64x*.* stuff only
supports PCIX mode. Hence, for a mixed PCI/PCIX, use the *_64s.*. It will
only run at 66Mhz, but seems to be much easier to use than the others. You
will need to maintain the same structure as in the *top.* file coming from
Xilinx if you are going to use their ucf files. Either that or change the
paths in your ucf files. I never use FPGA Express, so I'm not sure what
additional issues that may cause.


"owner" <kanglc@starhub.net.sg> wrote in message
news:265f36a.0401041841.14caff4a@posting.google.com...
Hi,

I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
NGDBUILD, the design, I encounter the following errors:

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'

The error continues for the whole bus width, and for other signals as
well.
I think the ucf file specifies the constraints using "/" to reference
the instance, but the core instantiates in a different way. There is a
file by the name of "pci_lc_i.vhd" which I found the instance
PCI_AD64_IO31_OFD instantiated as:

PCI_AD64_IO31_OFD : X_FF
port map(
.....

Does this mean I have to change the ucf file's constraint statements?
Can anyone in the group who has used xilinx logicore pci64 advice me
on this?

Any help is greatly appreciated.

Regards,
LC
Click to expand...
 
Something else I thought of is to make sure you are using the same compile
options as the example that comes with the core. i.e., don't loose your
hierarchy, don't balance the registers, don't insert buffers, etc.

"owner" <kanglc@starhub.net.sg> wrote in message
news:265f36a.0401041841.14caff4a@posting.google.com...
Hi,

I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
NGDBUILD, the design, I encounter the following errors:

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'

The error continues for the whole bus width, and for other signals as
well.
I think the ucf file specifies the constraints using "/" to reference
the instance, but the core instantiates in a different way. There is a
file by the name of "pci_lc_i.vhd" which I found the instance
PCI_AD64_IO31_OFD instantiated as:

PCI_AD64_IO31_OFD : X_FF
port map(
.....

Does this mean I have to change the ucf file's constraint statements?
Can anyone in the group who has used xilinx logicore pci64 advice me
on this?

Any help is greatly appreciated.

Regards,
LC
Click to expand...
 
Hi,

Were you able to implement the test design that
is provided with the core? That design is a
good design flow test.

Eric

owner wrote:
Hi,

I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
NGDBUILD, the design, I encounter the following errors:

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'

The error continues for the whole bus width, and for other signals as
well.
I think the ucf file specifies the constraints using "/" to reference
the instance, but the core instantiates in a different way. There is a
file by the name of "pci_lc_i.vhd" which I found the instance
PCI_AD64_IO31_OFD instantiated as:

PCI_AD64_IO31_OFD : X_FF
port map(
.....

Does this mean I have to change the ucf file's constraint statements?
Can anyone in the group who has used xilinx logicore pci64 advice me
on this?

Any help is greatly appreciated.

Regards,
LC
Click to expand...
 
It sounds like either:

a) You have changed one or more instance names within the design hierarchy so
that the paths 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' etc. are not valid, or

b) You have allowed the synthesis tool to change the design hierarchy by
flattening or grouping modules.

In my design I used the keep_hierachy XST synthesis attribute to tell XST to
leave the PCI core hierarchy alone when flattening my logic. I also did a
search/replace on the UCF file to change some instance names in the path so that
they match the instance names I wanted to use in my design.

Mark


owner wrote:
Hi,

I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
NGDBUILD, the design, I encounter the following errors:

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'

The error continues for the whole bus width, and for other signals as
well.
I think the ucf file specifies the constraints using "/" to reference
the instance, but the core instantiates in a different way. There is a
file by the name of "pci_lc_i.vhd" which I found the instance
PCI_AD64_IO31_OFD instantiated as:

PCI_AD64_IO31_OFD : X_FF
port map(
.....

Does this mean I have to change the ucf file's constraint statements?
Can anyone in the group who has used xilinx logicore pci64 advice me
on this?

Any help is greatly appreciated.

Regards,
LC
Click to expand...
 
Thanks for all your replies.

Mark,

Mark Schellhorn <mark@seawaynetworks.com> wrote in message news:<lMhKb.1496$k_.366272@news20.bellglobal.com>...
It sounds like either:

a) You have changed one or more instance names within the design hierarchy so
that the paths 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' etc. are not valid, or
Click to expand...
No, I have not modify the core's vhd files at all. In fact, take this
example above, the instance PCI-AD64 does not even exists. The "higher"
hierarchy instances - PCI_CORE/PCI_LC/ are correct. What I found is
an instance named PCI_AD64_IO31_OFD of a xilinx macro called X_FF
used under the component PCI_LC.

b) You have allowed the synthesis tool to change the design hierarchy by
flattening or grouping modules.

In my design I used the keep_hierachy XST synthesis attribute to tell XST to
leave the PCI core hierarchy alone when flattening my logic. I also did a
search/replace on the UCF file to change some instance names in the path so that
they match the instance names I wanted to use in my design.

Mark
Click to expand...
May be I should try XST first, using the ping example,
as suggested by Xilinx.

Thanks.

Regards,
LC
 
Hi,

Thanks everyone for your help.

I've found the problem. I was using a newer version of the
PCI logicore than that which my ISE can support. I don't
know why, but ngdbuild crashes with an "abnormal program
termination", saying it cannot find the ngo file.

After I downloaded an older version of the PCI core,
it works.

Regards,
LC

kanglc@starhub.net.sg (owner) wrote in message news:<265f36a.0401041841.14caff4a@posting.google.com>...
Hi,

I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
NGDBUILD, the design, I encounter the following errors:

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'

ERROR:NgdBuild:393 - Could not find INST(S)
'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
in design 'gefsc_top'. INST entry is 'INST
"PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'

The error continues for the whole bus width, and for other signals as
well.
I think the ucf file specifies the constraints using "/" to reference
the instance, but the core instantiates in a different way. There is a
file by the name of "pci_lc_i.vhd" which I found the instance
PCI_AD64_IO31_OFD instantiated as:

PCI_AD64_IO31_OFD : X_FF
port map(
.....

Does this mean I have to change the ucf file's constraint statements?
Can anyone in the group who has used xilinx logicore pci64 advice me
on this?

Any help is greatly appreciated.

Regards,
LC
Click to expand...
 
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