Xilinx: LOC'd IO internal to VHDL Module

[Andy Greensted]

Hi All,

XILINX Sparten2e - ISE5.1i

Is is possible to created a LOC'd IO connection for signals internal to a
VHDL module?

I've created a VHDL Module that has some normal port IO, however it also
contains some signals that are specific only to the module. These signals
need to be routed to FPGA pins - and therefore I'd like a LOC constraint on
them.

If I declare these signals in the entity port desciption, then just apply
the LOC attribute, the signals are still 'visible' on the module symbol.
They do not need to be. So can I internally LOC these signals? Hope that
makes sense. Here's an example with some VHDL of what I'm trying to do.

The input is dataIn - (Hopefully) LOC'd to pin 12. It's buffered, then
connected to a synchronizer (just a double flip flop). The only 'visible'
IO is dataOut and clk.

When I try this XST sees dataIn as unconnected, so ties it to ground. Then
during translate, it get's all upset because the IBUF is drived from the
IPAD, but is also tied :-( What's the official way of doing this?

Any help would really make my life A LOT easier. Cheers


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity interface is
Port ( clk : in std_logic;
dataOut : out std_logic);

end interface;

architecture Structural of interface is

component IBUF
port ( O : out std_logic;
I : in std_logic );
end component;

component SYNC
port ( dataIn : in std_logic;
dataOut : out std_logic;
clk : in std_logic );
end component;

attribute box_type : string;
attribute box_type of BUFG : component is "black_box";

attribute LOC : string;
attribute LOC of dataBuf : label is "P12";

signal dataIn : std_logic;
signal dataIn_b : std_logic;
begin

------------
-- Buffer --
------------
dataBuf : IBUF
port map ( I => dataIn,
O => dataIn_b);

----------------
-- Syncronize --
----------------
dataSync : SYNC
port map ( dataIn => dataIn_b,
dataOut => dataOut,
clk => clk);

end Structural;

 

[MM]

I don't think there is any official way of doing it in VHDL. All I/O's need
to be declared in the top-hierarchy file. The only way I can think of would
be through adding a probe pin in the FPGA Editor, however this probably
won't work either because your logic will get optimized out since if there
is no port, there is no need to consider that signal...

/Mikhail



"Andy Greensted" <ajg112@york.ac.uk> wrote in message
news:bl1p1s$9ml$1@pump1.york.ac.uk...

Hi All,

XILINX Sparten2e - ISE5.1i

Is is possible to created a LOC'd IO connection for signals internal to a
VHDL module?

I've created a VHDL Module that has some normal port IO, however it also
contains some signals that are specific only to the module. These signals
need to be routed to FPGA pins - and therefore I'd like a LOC constraint
on
them.

If I declare these signals in the entity port desciption, then just apply
the LOC attribute, the signals are still 'visible' on the module symbol.
They do not need to be. So can I internally LOC these signals? Hope that
makes sense. Here's an example with some VHDL of what I'm trying to do.

The input is dataIn - (Hopefully) LOC'd to pin 12. It's buffered, then
connected to a synchronizer (just a double flip flop). The only 'visible'
IO is dataOut and clk.

When I try this XST sees dataIn as unconnected, so ties it to ground. Then
during translate, it get's all upset because the IBUF is drived from the
IPAD, but is also tied :-( What's the official way of doing this?

Any help would really make my life A LOT easier. Cheers


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity interface is
Port ( clk : in std_logic;
dataOut : out std_logic);

end interface;

architecture Structural of interface is

component IBUF
port ( O : out std_logic;
I : in std_logic );
end component;

component SYNC
port ( dataIn : in std_logic;
dataOut : out std_logic;
clk : in std_logic );
end component;

attribute box_type : string;
attribute box_type of BUFG : component is "black_box";

attribute LOC : string;
attribute LOC of dataBuf : label is "P12";

signal dataIn : std_logic;
signal dataIn_b : std_logic;
begin

------------
-- Buffer --
------------
dataBuf : IBUF
port map ( I => dataIn,
O => dataIn_b);

----------------
-- Syncronize --
----------------
dataSync : SYNC
port map ( dataIn => dataIn_b,
dataOut => dataOut,
clk => clk);

end Structural;