Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN

R

Ronald Chung

Guest
I have spent three-four days on several XPLA3 CPLD boards that I've
designed (same boards) to determine why the JTAG is not working
properly. I cannot initialize the chain to "read" what devices are on
the boundary scan chain, nor will TDO change states. I can set
"levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of
the Xilinx IMPACT software.

I am using the Parallel IV cable and have read a few places it could
be cable length issues? Does ANYONE have any type of experience with
this? I've been wracking my brains out trying to figure out what's
wrong.

I am using a "home-made" cable because my PCB is used in embedded
application with limited space.

Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and
caps.

Any help is MUCH MUCH appreciated...

Thanks!
 
Ronald Chung wrote:
I have spent three-four days on several XPLA3 CPLD boards that I've
designed (same boards) to determine why the JTAG is not working
properly. I cannot initialize the chain to "read" what devices are on
the boundary scan chain, nor will TDO change states. I can set
"levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of
the Xilinx IMPACT software.

I am using the Parallel IV cable and have read a few places it could
be cable length issues? Does ANYONE have any type of experience with
this? I've been wracking my brains out trying to figure out what's
wrong.

I am using a "home-made" cable because my PCB is used in embedded
application with limited space.

Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and
caps.

Any help is MUCH MUCH appreciated...

Thanks!
Click to expand...
Try to add an 1K pull-up on TDO and let me know if that's better.

Laurent
www.amontec.com
 
Amontec Team, Laurent Gauch wrote:

Ronald Chung wrote:

I have spent three-four days on several XPLA3 CPLD boards that I've
designed (same boards) to determine why the JTAG is not working
properly. I cannot initialize the chain to "read" what devices are on
the boundary scan chain, nor will TDO change states. I can set
"levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of
the Xilinx IMPACT software.

I am using the Parallel IV cable and have read a few places it could
be cable length issues? Does ANYONE have any type of experience with
this? I've been wracking my brains out trying to figure out what's
wrong.

I am using a "home-made" cable because my PCB is used in embedded
application with limited space.

Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and
caps.

Any help is MUCH MUCH appreciated...

Thanks!


Try to add an 1K pull-up on TDO and let me know if that's better.

Laurent
www.amontec.com

place the pull-up on 5V (if you have a 5V)
Click to expand...

Laurent
www.amontec.com
 
Amontec Team, Laurent Gauch wrote:

Amontec Team, Laurent Gauch wrote:

Ronald Chung wrote:

I have spent three-four days on several XPLA3 CPLD boards that I've
designed (same boards) to determine why the JTAG is not working
properly. I cannot initialize the chain to "read" what devices are on
the boundary scan chain, nor will TDO change states. I can set
"levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of
the Xilinx IMPACT software.

I am using the Parallel IV cable and have read a few places it could
be cable length issues? Does ANYONE have any type of experience with
this? I've been wracking my brains out trying to figure out what's
wrong.

I am using a "home-made" cable because my PCB is used in embedded
application with limited space.

Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and
caps.

Any help is MUCH MUCH appreciated...

Thanks!



Try to add an 1K pull-up on TDO and let me know if that's better.

Laurent
www.amontec.com

place the pull-up on 5V (if you have a 5V)

Laurent
www.amontec.com

OOPS, try to download xpla_programmer.exe from our webpage
Click to expand...
http://www.amontec.com/chameleon_xilinxcableiii.shtml

That's the old programmer provided by Philips for Xilinx.
You will find the schematic of the how to connect the PC parallel port
to the XPLA JTAG PORT.

PS: Are you sure about the PIN PORT_EN of your XPLA, when your are in
JTAG mode, these pin must be at '1' logic.

Laurent
www.amontec.com
 
Thanks for the help...

I finally figured out there was a pin-mis-wire on my schematics...
hidden in all the hierarchy. Thought I had checked the wiring, but
must have missed it...

Things are configuring now.

Just a note for those out there.... if you get erratic behaviour
because the JTAG sometimes will and/or will not initialize the chain,
it could be due to swapping TDI and TCK.

RC
 
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