Xilinx ISE6.1 Verilog `define macro?

[Hakjs]

I tried something like

`define MINIMUM2(x,y) (((x)<)?(x)y))
`define MINIMUM3(x,y,z) `MINIMUM2(`MINIMUM2(x,y),z)

This worked fine in Modelsim Verilog simulator, but Xilinx ISE6.1i's
XST (synthesis) didn't seem to like it...

Am I doing something wrong?