Xilinx ISE Webpack and Pipeline Optimization

[Tim Wescott]

Here's a naive question, from a sometime FPGA user:

A long time ago, a friend of mine who does _real_ digital design work
was telling me how cool the (then new) Mentor tools were, because you
could do a whole bunch of natural-looking combinational Verilog code in
a module, then at the very end you could put in a bunch of register
delays, and the tools would figure out how to distribute the delays in
your combinational code to get a nicely pipelined bit of logic.

Has this nifty technology migrated into Xilinx tools? Or if I need
pipelining, do I need to figure it out myself?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

 

[Rob Gaddi]

On 8/3/2010 10:25 AM, Tim Wescott wrote:

Here's a naive question, from a sometime FPGA user:

A long time ago, a friend of mine who does _real_ digital design work
was telling me how cool the (then new) Mentor tools were, because you
could do a whole bunch of natural-looking combinational Verilog code in
a module, then at the very end you could put in a bunch of register
delays, and the tools would figure out how to distribute the delays in
your combinational code to get a nicely pipelined bit of logic.

Has this nifty technology migrated into Xilinx tools? Or if I need
pipelining, do I need to figure it out myself?

Theoretically yes, practically I've had great difficulty getting the
tools to distribute any more than one level of pipeline delay.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Manny]

On Aug 3, 6:25 pm, Tim Wescott <t...@seemywebsite.com> wrote:

Here's a naive question, from a sometime FPGA user:

A long time ago, a friend of mine who does _real_ digital design work
was telling me how cool the (then new) Mentor tools were, because you
could do a whole bunch of natural-looking combinational Verilog code in
a module, then at the very end you could put in a bunch of register
delays, and the tools would figure out how to distribute the delays in
your combinational code to get a nicely pipelined bit of logic.

Has this nifty technology migrated into Xilinx tools?  Or if I need
pipelining, do I need to figure it out myself?

You have to always be cautious of what the tools can or can not do for
you. My experience tells me that cheap tools are better off fed the
design with a spoon. Then comes a host of other problems to do with
bugs everywhere, e.g. a design with a MACC has to be broken into
separate multiply and accumulate blocks and then retimed. Pure joy!

-Momo

 

[Steve Pope]

On Aug 3, 6:25 pm, Tim Wescott <t...@seemywebsite.com> wrote:

Here's a naive question, from a sometime FPGA user:

A long time ago, a friend of mine who does _real_ digital design work
was telling me how cool the (then new) Mentor tools were, because you
could do a whole bunch of natural-looking combinational Verilog code in
a module, then at the very end you could put in a bunch of register
delays, and the tools would figure out how to distribute the delays in
your combinational code to get a nicely pipelined bit of logic.

Has this nifty technology migrated into Xilinx tools?  Or if I need
pipelining, do I need to figure it out myself?

Register retiming. All the synthesizers do this.

Steve

 

[Andy]

But how many re-time over more than one clock cycle? Many can only
move logic +/- 1 clock cycle, and some don't do it unless the original
design won't meet timing.

Andy

 

[emeb]

On Aug 3, 1:40 pm, spop...@speedymail.org (Steve Pope) wrote:

On Aug 3, 6:25 pm, Tim Wescott <t...@seemywebsite.com> wrote:

Here's a naive question, from a sometime FPGA user:

A long time ago, a friend of mine who does _real_ digital design work
was telling me how cool the (then new) Mentor tools were, because you
could do a whole bunch of natural-looking combinational Verilog code in
a module, then at the very end you could put in a bunch of register
delays, and the tools would figure out how to distribute the delays in
your combinational code to get a nicely pipelined bit of logic.

Has this nifty technology migrated into Xilinx tools?  Or if I need
pipelining, do I need to figure it out myself?

Register retiming.  All the synthesizers do this.

My favorite tool for this was something Synopsys sold years ago called
'Module Compiler'. Apparently they bought another company that
actually made this, but my first exposure was at Synopsys. It used a
'Verilog-like' language to specify the logical & mathematical
operations without any pipelining. The only registers you'd put in
explicitly were those required for state (like accumulators, state
machines, etc). It used the target library capabilities to do all the
pipelining for you, as well as optimizing the logic & math - sort of a
precursor to what became Physical Synthesis. It would spit out a gate-
level netlist for the P/R tools and behavioral Verilog for
verification. Amazing stuff.

Apparently most of Module Compiler was rolled into Design Compiler a
while back. Don't know what became of it beyond that.

Eric