Xilinx ISE schematic design

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Hi there!

I am trying to design some module (special array multiplier) and due to its
interconnect complexity and number of irregularly structured internal
components, I have started designing it in the schematic editor of Xilinx
ISE. I have designed its components in VHDL and have created appropriate
schematic symbols for them and now am trying to connect multiple instances
of them.

My problem is as follows: the entity declaration of one component, say a NOT
gate, is:

entity not_ent is
Generic (Load : integer := 1);
Port (inp : in std_logic;
outp : out std_logic);
end not_ent;

What I want to do is, when I use a schematic instance of the NOT component,
I also want to somehow assign a value to its generic attribute (i.e. its
drive Load). If I had been doing it with VHDL, I would write something like:

NOT_1: not_ent generic map (Load => 1) port map (inp => inp, outp => outp);

but I cannot do generic map in the schematic design. Is there some way to
include the generic attributes in the schematic design or not?


Sorry for the large post

Best regards,
chris