Xilinx Ise ignores module's parameter list in Verilog

H

hhanff

Guest
Hello!

My native language is VHDL. Thus I'm in trouble instantiating the
following Xilinx Module.
Basically I want to instantiate a Block RAM as declared in the Spartan
6 libraries guide.

// RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable
Synchronous Block RAM
// Spartan-6
// Xilinx HDL Language Template, version 13.2
RAMB8BWER #(
// DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9
or 18; If RAM_MODE="SDP": 36'
.DATA_WIDTH_A(4), // <- ****** BUS WIDTH SET TO = 4 ******
.DATA_WIDTH_B(4), // <- ****** BUS WIDTH SET TO = 4 ******
// DOA_REG/DOB_REG: Optional output register (0 or 1)
.DOA_REG(0),
.DOB_REG(0),
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
// INITP_00 to INITP_03: Initial memory contents.
[....]
..INIT_FILE("NONE"), //
Do not modify
// RAM_MODE: "SDP" or "TDP"
.RAM_MODE("TDP"),
// RSTTYPE: "SYNC" or "ASYNC"
.RSTTYPE("SYNC"),
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
// SIM_COLLISION_CHECK: Collision check enable "ALL",
"WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
.SIM_COLLISION_CHECK("NONE"),
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or
"NO_CHANGE"
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
RAMB8BWER_inst_info_fifo(
// Port A Data: 16-bit (each) output: Port A data
.DOADO(), // 16-bit output: A port data/LSB data
output
.DOPADOP(), // 2-bit output: A port parity/LSB parity
output
// Port B Data: 16-bit (each) output: Port B data
.DOBDO({length_info_16}), // 16-bit output: B port
data/MSB data output
.DOPBDOP(), // 2-bit output: B port parity/MSB parity
output
// Port A Address/Control Signals: 13-bit (each) input: Port A
address and control signals (write port
// when RAM_MODE="SDP")
.ADDRAWRADDR({7'h0, wr_info_pointer}), // 13-bit input: A port
address/Write address input
.CLKAWRCLK(clk), // 1-bit input: A port clock/Write clock
input
.ENAWREN(1'b1), // 1-bit input: A port enable/Write
enable input
.REGCEA(1'b1), // 1-bit input: A port register enable
input
.RSTA(1'b0), // 1-bit input: A port set/reset
input
.WEAWEL({1'b0,write_length_info & (~info_full) |
initialize_memories}), // 2-bit input: A port write enable
input
// Port A Data: 16-bit (each) input: Port A data
.DIADI({12'h0,len_cnt &
{4{~initialize_memories}}}), // 16-bit input: A port data/
LSB data input
.DIPADIP(), // 2-bit input: A port parity/LSB parity
input
// Port B Address/Control Signals: 13-bit (each) input: Port B
address and control signals (read port
// when RAM_MODE="SDP")
.ADDRBRDADDR({7'h0, rd_info_pointer}), // 13-bit input: B port
address/Read address input
.CLKBRDCLK(clk), // 1-bit input: B port clock/Read clock
input
.ENBRDEN(1'b1), // 1-bit input: B port enable/Read
enable input
.REGCEBREGCE(1'b1), // 1-bit input: B port register enable/
Register enable input
.RSTBRST(1'b0), // 1-bit input: B port set/reset input
.WEBWEU(2'b0), // 2-bit input: B port write enable
input
// Port B Data: 16-bit (each) input: Port B data
.DIBDI(16'h0), // 16-bit input: B port data/MSB data
input
.DIPBDIP(2'h0) // 2-bit input: B port parity/MSB parity
input
);

For my understanding I'm telling the module to use 4 bit wide data
ports. Nevertheless, DOBDO will be 16 bit wide...
Where is my mistake???
 
hhanff wrote:
Hello!

My native language is VHDL. Thus I'm in trouble instantiating the
following Xilinx Module.
Basically I want to instantiate a Block RAM as declared in the Spartan
6 libraries guide.

// RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable
Synchronous Block RAM
// Spartan-6
// Xilinx HDL Language Template, version 13.2
RAMB8BWER #(
// DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9
or 18; If RAM_MODE="SDP": 36'
.DATA_WIDTH_A(4), // <- ****** BUS WIDTH SET TO = 4 ******
.DATA_WIDTH_B(4), // <- ****** BUS WIDTH SET TO = 4 ******
// DOA_REG/DOB_REG: Optional output register (0 or 1)
.DOA_REG(0),
.DOB_REG(0),
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
// INITP_00 to INITP_03: Initial memory contents.
[....]
.INIT_FILE("NONE"), //
Do not modify
// RAM_MODE: "SDP" or "TDP"
.RAM_MODE("TDP"),
// RSTTYPE: "SYNC" or "ASYNC"
.RSTTYPE("SYNC"),
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
// SIM_COLLISION_CHECK: Collision check enable "ALL",
"WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
.SIM_COLLISION_CHECK("NONE"),
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or
"NO_CHANGE"
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
RAMB8BWER_inst_info_fifo(
// Port A Data: 16-bit (each) output: Port A data
.DOADO(), // 16-bit output: A port data/LSB data
output
.DOPADOP(), // 2-bit output: A port parity/LSB parity
output
// Port B Data: 16-bit (each) output: Port B data
.DOBDO({length_info_16}), // 16-bit output: B port
data/MSB data output
.DOPBDOP(), // 2-bit output: B port parity/MSB parity
output
// Port A Address/Control Signals: 13-bit (each) input: Port A
address and control signals (write port
// when RAM_MODE="SDP")
.ADDRAWRADDR({7'h0, wr_info_pointer}), // 13-bit input: A port
address/Write address input
.CLKAWRCLK(clk), // 1-bit input: A port clock/Write clock
input
.ENAWREN(1'b1), // 1-bit input: A port enable/Write
enable input
.REGCEA(1'b1), // 1-bit input: A port register enable
input
.RSTA(1'b0), // 1-bit input: A port set/reset
input
.WEAWEL({1'b0,write_length_info & (~info_full) |
initialize_memories}), // 2-bit input: A port write enable
input
// Port A Data: 16-bit (each) input: Port A data
.DIADI({12'h0,len_cnt &
{4{~initialize_memories}}}), // 16-bit input: A port data/
LSB data input
.DIPADIP(), // 2-bit input: A port parity/LSB parity
input
// Port B Address/Control Signals: 13-bit (each) input: Port B
address and control signals (read port
// when RAM_MODE="SDP")
.ADDRBRDADDR({7'h0, rd_info_pointer}), // 13-bit input: B port
address/Read address input
.CLKBRDCLK(clk), // 1-bit input: B port clock/Read clock
input
.ENBRDEN(1'b1), // 1-bit input: B port enable/Read
enable input
.REGCEBREGCE(1'b1), // 1-bit input: B port register enable/
Register enable input
.RSTBRST(1'b0), // 1-bit input: B port set/reset input
.WEBWEU(2'b0), // 2-bit input: B port write enable
input
// Port B Data: 16-bit (each) input: Port B data
.DIBDI(16'h0), // 16-bit input: B port data/MSB data
input
.DIPBDIP(2'h0) // 2-bit input: B port parity/MSB parity
input
);

For my understanding I'm telling the module to use 4 bit wide data
ports. Nevertheless, DOBDO will be 16 bit wide...
Where is my mistake???
Click to expand...
This parameter does not change the port width, only the number of active
bits. If you look at the port descriptions, they are always noted as
16 bits regardless of the actual parameters. A quick look into the
simulation model proves this out. You can find the model in your
ISE installation directory at:
ISE\verilog\src\unisims\RAMB8BWER.v

The Libraries guide suggests inference for block RAM, and I would agree.
If you're not confident in your ability to infer the RAM you need, then
my other suggestion is to let CoreGen do the work for you. However
there are language templates in ISE that show you how to infer block
RAM.

-- Gabor
 
On 5 Dez., 22:51, Gabor <ga...@szakacs.invalid> wrote:
hhanff wrote:
Hello!

My native language is VHDL. Thus I'm in trouble instantiating the
following Xilinx Module.
Basically I want to instantiate a Block RAM as declared in the Spartan
6 libraries guide.

   // RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable
Synchronous Block RAM
   //            Spartan-6
   // Xilinx HDL Language Template, version 13.2
   RAMB8BWER #(
      // DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9
or 18; If RAM_MODE="SDP": 36'
      .DATA_WIDTH_A(4), // <- ****** BUS WIDTH SET TO   = 4 ******
      .DATA_WIDTH_B(4), // <- ****** BUS WIDTH SET TO   = 4 ******
      // DOA_REG/DOB_REG: Optional output register (0 or 1)
      .DOA_REG(0),
      .DOB_REG(0),
      // EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
      .EN_RSTRAM_A("TRUE"),
      .EN_RSTRAM_B("TRUE"),
      // INITP_00 to INITP_03: Initial memory contents.
[....]
.INIT_FILE("NONE"),                                                               //
Do not modify
      // RAM_MODE: "SDP" or "TDP"
      .RAM_MODE("TDP"),
      // RSTTYPE: "SYNC" or "ASYNC"
      .RSTTYPE("SYNC"),
      // RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
      .RST_PRIORITY_A("CE"),
      .RST_PRIORITY_B("CE"),
      // SIM_COLLISION_CHECK: Collision check enable "ALL",
"WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
      .SIM_COLLISION_CHECK("NONE"),
      // SRVAL_A/SRVAL_B: Set/Reset value for RAM output
      .SRVAL_A(18'h00000),
      .SRVAL_B(18'h00000),
      // WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or
"NO_CHANGE"
      .WRITE_MODE_A("WRITE_FIRST"),
      .WRITE_MODE_B("WRITE_FIRST")
   )
   RAMB8BWER_inst_info_fifo(
      // Port A Data: 16-bit (each) output: Port A data
      .DOADO(),             // 16-bit output: A port data/LSB data
output
      .DOPADOP(),         // 2-bit output: A port parity/LSB parity
output
      // Port B Data: 16-bit (each) output: Port B data
      .DOBDO({length_info_16}),             // 16-bit output: B port
data/MSB data output
      .DOPBDOP(),         // 2-bit output: B port parity/MSB parity
output
      // Port A Address/Control Signals: 13-bit (each) input: Port A
address and control signals (write port
      // when RAM_MODE="SDP")
      .ADDRAWRADDR({7'h0, wr_info_pointer}), // 13-bit input: A port
address/Write address input
      .CLKAWRCLK(clk),     // 1-bit input: A port clock/Write clock
input
      .ENAWREN(1'b1),         // 1-bit input: A port enable/Write
enable input
      .REGCEA(1'b1),           // 1-bit input: A port register enable
input
      .RSTA(1'b0),               // 1-bit input: A port set/reset
input
      .WEAWEL({1'b0,write_length_info & (~info_full) |
initialize_memories}),           // 2-bit input: A port write enable
input
      // Port A Data: 16-bit (each) input: Port A data
      .DIADI({12'h0,len_cnt &
{4{~initialize_memories}}}),             // 16-bit input: A port data/
LSB data input
      .DIPADIP(),         // 2-bit input: A port parity/LSB parity
input
      // Port B Address/Control Signals: 13-bit (each) input: Port B
address and control signals (read port
      // when RAM_MODE="SDP")
      .ADDRBRDADDR({7'h0, rd_info_pointer}), // 13-bit input: B port
address/Read address input
      .CLKBRDCLK(clk),     // 1-bit input: B port clock/Read clock
input
      .ENBRDEN(1'b1),         // 1-bit input: B port enable/Read
enable input
      .REGCEBREGCE(1'b1), // 1-bit input: B port register enable/
Register enable input
      .RSTBRST(1'b0),         // 1-bit input: B port set/reset input
      .WEBWEU(2'b0),           // 2-bit input: B port write enable
input
      // Port B Data: 16-bit (each) input: Port B data
      .DIBDI(16'h0),             // 16-bit input: B port data/MSB data
input
      .DIPBDIP(2'h0)          // 2-bit input: B port parity/MSB parity
input
   );

For my understanding I'm telling the module to use 4 bit wide data
ports. Nevertheless, DOBDO will be 16 bit wide...
Where is my mistake???

This parameter does not change the port width, only the number of active
bits.  If you look at the port descriptions, they are always noted as
16 bits regardless of the actual parameters.  A quick look into the
simulation model proves this out.  You can find the model in your
ISE installation directory at:
ISE\verilog\src\unisims\RAMB8BWER.v

The Libraries guide suggests inference for block RAM, and I would agree.
If you're not confident in your ability to infer the RAM you need, then
my other suggestion is to let CoreGen do the work for you.  However
there are language templates in ISE that show you how to infer block
RAM.

-- Gabor
Click to expand...
Thanks. That helped.
 
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