Xilinx ISE ignores Max Fanout

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I had been working with Xilinx ISE 12.4 for a while trying to improve th
performance of a SPARC based processor.

Till now, I was always and stopping at the "Synthesize - XST" step. I foun
that going into the "Process Properties" -> "Xilinx Specific Options" fo
the synthesis process and reducing Max Fanout from 500, down to betwee
40-16 got me timing closure with not too much additional area. Which i
nice.

Now, I need to generate a bitfile and therefore need a proper Xilin
license. Unfortunately, I have access only to a license for ISE 11 (from m
university).

So, I installed 11.1, set the max fanout the same way as earlier, and r
ran XST. I now find that this max fanout is ignored (lots of FFs wit
fanouts > 100 and correspondingly large delays) and this causes timin
requirements to not be met.

I googled around, and found a couple of suggestions:
1. Switch off "Resource Sharing" under "HDL Options"
2. Switch off "Equivalent Register Removal" under "Xilinx Specifi
Options"
3. Make sure "Register Duplication" is on (which it always was)

At least #2 seemed to make sense because I felt that equivalent registe
removal conflicts with the goal of max fanout. So I did all this.

=> Still, max fanout seems to be ignored.

I have also looked at the Xilinx Constraints Guide and it does not clearl
tell when global max fanout is ignored. In fact it goes into detai
explaining an example where a module specific max fanout (defined in th
xcf file) is ignored, but it says nothing about global max fanout. It doe
say that really low values are not always followed. But a fanout of 10
where the max defined as 16 seems a bit too much.

So why does this happen? There is no difference between the sources I use
for 12.4 and am now using for 11.1.

More importantly, how can I fix this?



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