Xilinx ISE ERRORS HDLCompilers:108

Z

zhangbert

Guest
I am running the Xilinx ISE Release Version: 10.1.03. I am making a validation for an ARM926EJS IP core. At the step of check syntax, a series of such errors as "HDLCompilers:108 - 'a926InstrCache.v' line 3051 Part-select of scalar wire 'sNSeqVAIndex' is illegal" occurs, but when I changed to running the project including the same source files in Altera Quartus, there aren't any syntax errors. It bothering me very well. Could anyone help me? The part of program is as follows
module ...
..
wire [ 4: 2] PWFBWord
wire [ 3: 0] PWFBByteSel
..
a926CacheFB uFB
.CClk (CClk)
.CnReset (CnReset)

.PWFBFull (PWFBFull)
// .PWFBWord (PWFBWord)
.PWFBWord (PWFBWord[4:2])
// .PWFBByteSel (PWFBByteSel)
.PWFBByteSel (PWFBByteSel[3:0])
.PWFBWriteback (PWFBWriteback)
.PWFBD (PWFBD)
// .PWFBD (PWFBD[31:0])

.BIURD (BIURD)
// .BIURD (BIURD[31:0])
.CACHEBIUReady (CACHEBIUReady)

.sMemReq (sMemReq)
// .sVA (sVA)
.sVA (sVA[4:2])
.sNSeqVA (sNSeqVA[24:5])
.RawMVA (RawMVA[31:25])
.LfVA (LfVA[24:5])
.LfMVA (LfMVA[31:25])
.LfWay (LfWayFB[3:0])

.FBHit (FBHit)
.FBWordHit (FBWordHit)
.FBFull (FBFull)
.FBFilling (FBFilling)
.FBFill (FBFill)
.FBDirtyLower (FBDirtyLower)
.FBDirtyUpper (FBDirtyUpper)
.FBDrain (FBDrain)
.DATAFBUpperSel (DATAFBUpperSel)
.LFStart (LFStart)

.CP15InvalAll (CP15InvalAll)
.CP15InvalFB (CP15InvalFB)
.CNoLinefill (CNoLinefill)

.FBWD0 (FBWD0[31:0])
.FBWD1 (FBWD1[31:0])
.FBWD2 (FBWD2[31:0])
.FBWD3 (FBWD3[31:0])
.FBRD (FBRD[31:0]
)

The errors are very strange. Once the part-select index among the brackets of each variable is deleted in the instantiation of a926CacheFB module, the corresponding error will disappear. I am not sure whether the method is useful to eliminate the errors while not to change its functions because of the complexity of the project. I am sorry if I made a unclear explanation of my question. Please excuse me for my poor English.
 
On Oct 29, 7:17 am, zhangbert <u...@compgroups.net/> wrote:
I am running the Xilinx ISE Release Version: 10.1.03. I am making a validation for an ARM926EJS IP core. At the step of check syntax, a series of such errors as "HDLCompilers:108 - 'a926InstrCache.v' line 3051 Part-select of scalar wire 'sNSeqVAIndex' is illegal" occurs, but when I changed to running the project including the same source files in Altera Quartus, there aren't any syntax errors. It bothering me very well. Could anyone help me? The part of program is as follows:
module ...;
...
wire   [ 4: 2] PWFBWord;
wire   [ 3: 0] PWFBByteSel;
...
a926CacheFB uFB(
  .CClk           (CClk),
  .CnReset        (CnReset),

  .PWFBFull       (PWFBFull),
//  .PWFBWord       (PWFBWord),
  .PWFBWord       (PWFBWord[4:2]),
//  .PWFBByteSel    (PWFBByteSel),
  .PWFBByteSel    (PWFBByteSel[3:0]),
  .PWFBWriteback  (PWFBWriteback),
  .PWFBD          (PWFBD),
//  .PWFBD          (PWFBD[31:0]),

  .BIURD          (BIURD),
//  .BIURD          (BIURD[31:0]),
  .CACHEBIUReady  (CACHEBIUReady),

  .sMemReq        (sMemReq),
//  .sVA            (sVA),
  .sVA            (sVA[4:2]),
  .sNSeqVA        (sNSeqVA[24:5]),
  .RawMVA         (RawMVA[31:25]),
  .LfVA           (LfVA[24:5]),
  .LfMVA          (LfMVA[31:25]),
  .LfWay          (LfWayFB[3:0]),

  .FBHit          (FBHit),
  .FBWordHit      (FBWordHit),
  .FBFull         (FBFull),
  .FBFilling      (FBFilling),
  .FBFill         (FBFill),
  .FBDirtyLower   (FBDirtyLower),
  .FBDirtyUpper   (FBDirtyUpper),
  .FBDrain        (FBDrain),
  .DATAFBUpperSel (DATAFBUpperSel),
  .LFStart        (LFStart),

  .CP15InvalAll   (CP15InvalAll),
  .CP15InvalFB    (CP15InvalFB),
  .CNoLinefill    (CNoLinefill),

  .FBWD0          (FBWD0[31:0]),
  .FBWD1          (FBWD1[31:0]),
  .FBWD2          (FBWD2[31:0]),
  .FBWD3          (FBWD3[31:0]),
  .FBRD           (FBRD[31:0])
);

   The errors are very strange. Once the part-select index among the brackets of each variable is deleted in the instantiation of a926CacheFB module, the corresponding error will disappear. I am not sure whether the method is useful to eliminate the errors while not to change its functions because of the complexity of the project. I am sorry if I made a unclear explanation of my question. Please excuse me for my poor English.
Click to expand...
You didn't include the full file, so it isn't possible to determine
which line is 3051. The code portion that you posted doesn't have
anything called "sNSeqVAIndex" and the closest item that I could find
was

.sNSeqVA (sNSeqVA[24:5]),

Was the "sNSeqVA" port on the "a926CacheFB" module defined as [19:0]?
Does the wire or reg "sNSeqVA" that drives this port have a size that
is at least [24:0]?

It could be a XST bug that has since been fixed. You are using 10.1.3
and the latest software is 12.3.

BTW, Your english is perfect.

Ed McGettigan
--
Xilinx Inc.
 
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