Xilinx ISE 9.1i problem.

[Daniel]

Hi,
I'm working with ISE 9.1i and it seems to be removing some LOCed
pins.
I have a top level with a grop of input pins (xBBIO_N0...xBBIO_N31)
and output pins (xPMC_N0...xPMC_N31). All I do in my design is to add
a component who does an assignation (31 times in a "for generate"):

IBUF(i=>xBBIO_N0,o=>xPMC_N0)

When PAR finishes and I open the CSV file, I see that all those
signals are are gone!.

In the Map report I see a suspicious warning;
WARNING:MapLib:701 - Signal xBBIO_N0 conected to top level port
xBBIO_N0 has been removed

The Xilinx´s knowledge database refers to ISE 8.1 but I'm using ISE
9.1!!.

There is a thread (http://newsgroups.derkeiler.com/Archive/Comp/
comp.arch.fpga/2005-09/msg00169.html) about this problem but none of
those solutions worked. Because I cant set "AD I/O buffers" option
(other errors appear in that case).


Am I forgetting a constraint or something?.

Regards,
Daniel.

 

[Symon]

Daniel wrote:

Hi,
I'm working with ISE 9.1i and it seems to be removing some LOCed
pins.


Am I forgetting a constraint or something?.

Dear Daniel,

Probably not. My guess is your logic has been optimised away.
Check that the inputs to your circuit are being driven.
HTH., Syms.

 

[Daniel]

Hi,
finally I could solve the problem. I used an IBUF por the input port
and an OBUFT for the output. I also had to force a PULLUP in UCF file
for output pins... don`t really know why... no either know why a OBUFT
and not just an OBUF, but I solved!.
Thanks.

Daniel.

On Mar 27, 9:39 pm, "Symon" <symon_bre...@hotmail.com> wrote:

Daniel wrote:
Hi,
I'm working with ISE 9.1i and it seems to be removing some LOCed
pins.

Am I forgetting a constraint or something?.

Dear Daniel,
Probably not. My guess is your logic has been optimised away.
Check that the inputs to your circuit are being driven.
HTH., Syms.