Xilinx ISE 6.3 confusion for CPLD logic

My VHDL project has out grown a XC95108 CPLD, so I'll be using a
XC95144 instead. After running the ISE synthesizer and fitter, all of
the XC95144's Function Block Inputs are used. Using exhaustive fit
mode, 92% of the function block inputs are used. This still doesn't
leave much room for additional features. I then told ISE to use a
XC95144XL, instead. Only 64% of the function block inputs are used, and
the other resources look good, too. Even though the XL is a 3.3 volt
chip, it's 5 volt tolerant, so it should work. The odd thing is that
the XL version uses _8 more_ flip flops than the standard version, and
the timing report shows that the XL is faster than the std part, even
though I selected 10 ns speed grade for both parts. I haven't
simulated both chips yet. There's lots of information in the Fitter
Report, but I don't know what I should be looking for. I'm a bit
overwhelmed. So far, the Xilinx docs haven't helped.

 

[Mike Treseler]

vze24h5m@verizon.net wrote:

My VHDL project has out grown a XC95108 CPLD, so I'll be using a
XC95144 instead. After running the ISE synthesizer and fitter, all of
the XC95144's Function Block Inputs are used. Using exhaustive fit
mode, 92% of the function block inputs are used. This still doesn't
leave much room for additional features. I then told ISE to use a
XC95144XL, instead. Only 64% of the function block inputs are used, and
the other resources look good, too.

I would conclude that the XL
has more function blocks.
Does it?

The odd thing is that
the XL version uses _8 more_ flip flops than the standard version, and
the timing report shows that the XL is faster than the std part, even
though I selected 10 ns speed grade for both parts.

Not odd. These are different parts and
synthesis is allowed to trade gates for flops.

I haven't
simulated both chips yet.

I wouldn't worry about gate level sims,
but I would make sure the rtl code is
functional before squeezing it into a device.

-- Mike Treseler

 

[Isaac Bosompem]

Mike Treseler wrote:

I wouldn't worry about gate level sims,
but I would make sure the rtl code is
functional before squeezing it into a device.

-- Mike Treseler

Sorry I am still somewhat of a newbie. But why would someone perform
gate level simulation if their RTL design is functional?

-Isaac

 

[Allan Herriman]

On 21 Feb 2006 22:04:26 -0800, "Isaac Bosompem" <x86asm@gmail.com>
wrote:

Mike Treseler wrote:

I wouldn't worry about gate level sims,
but I would make sure the rtl code is
functional before squeezing it into a device.

-- Mike Treseler

Sorry I am still somewhat of a newbie. But why would someone perform
gate level simulation if their RTL design is functional?

1. A designer might have an background in ASIC design. It's hard to
let go of those old habits.

2. A designer might suspect a tool bug (in either the synthesiser or
back end tools). These happen more often that you'd like.
Back in the day, XST would spit out EDIF, so you could look for XST
bugs that way instead, but Xilinx stopped it from doing that.

3. A designer may wish to perform a simulation with back-annotated
delays. This would only be necessary if the designer considered that
STA (Static Timing Analysis) was inadequate for some reason. (Can't
think of a good reason right now, assuming the constraints are
correct.)

Regards,
Allan