Xilinx ISE 6.1i

[Jake Janovetz]

Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled
it under 6.1i (from 5.2i, previously). It failed timing by about 20%
where it previously passed.

Anyone have similar "luck" ?

Jake

 

[Antti Lukats]

jakespambox@yahoo.com (Jake Janovetz) wrote in message news:<d6ad3144.0309151854.54e599c2@posting.google.com>...

Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled
it under 6.1i (from 5.2i, previously). It failed timing by about 20%
where it previously passed.

Anyone have similar "luck" ?

Jake

where did you get 6.1i ? dont see it been released on xilinx website?
antti

 

[Giuseppeł]

Had you regenerate the ucf file with PACE?
I regenerate copletely this file and the time constrain return to the
original (5.2 version)

Bye
Giuseppe

"Jake Janovetz" <jakespambox@yahoo.com> ha scritto nel messaggio
news:d6ad3144.0309151854.54e599c2@posting.google.com...

Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled
it under 6.1i (from 5.2i, previously). It failed timing by about 20%
where it previously passed.

Anyone have similar "luck" ?

Jake

 

[Giuseppeł]

Also this morning I saw that there is the first service pack available to
the web for 6.1 version

Bye
Giuseppe

"Giuseppeł" <miaooaim@inwind.it> ha scritto nel messaggio
news:bk6kph$qb16m$1@ID-61213.news.uni-berlin.de...

Had you regenerate the ucf file with PACE?
I regenerate copletely this file and the time constrain return to the
original (5.2 version)

Bye
Giuseppe

"Jake Janovetz" <jakespambox@yahoo.com> ha scritto nel messaggio
news:d6ad3144.0309151854.54e599c2@posting.google.com...
Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled
it under 6.1i (from 5.2i, previously). It failed timing by about 20%
where it previously passed.

Anyone have similar "luck" ?

Jake

 

[Lorenzo]

"Jake Janovetz" <jakespambox@yahoo.com> ha scritto nel messaggio
news:d6ad3144.0309151854.54e599c2@posting.google.com...

Has anyone tried 6.1i yet? I took a Spartan IIE design
and compiled
it under 6.1i (from 5.2i, previously). It failed timing
by about 20%
where it previously passed.

You are lucky! I have just upgraded from WebPack 4.2 to 5.2, and a SpartanII
project that previuosly worked, now it doesn't even map...

map report with 4.2:

Design Information
------------------
Command Line : map -p xc2s100-tq144-5 -cm area -k 4 -c 100 -tx off
main.ngd
Target Device : x2s100
Target Package : tq144
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.58 $
Mapped Date : Wed Jul 23 16:28:06 2003

Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Number of Slices: 1,198 out of 1,200 99%
Number of Slices containing
unrelated logic: 269 out of 1,198 22%
Number of Slice Flip Flops: 1,127 out of 2,400 46%
Total Number 4 input LUTs: 2,133 out of 2,400 88%
Number used as LUTs: 1,974
Number used as a route-thru: 159
Number of bonded IOBs: 54 out of 92 58%
IOB Flip Flops: 14
Number of Tbufs: 416 out of 1,280 32%
Number of Block RAMs: 5 out of 10 50%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 2 out of 4 50%
Total equivalent gate count for design: 107,305
Additional JTAG gate count for IOBs: 2,688



map report with 5.2:

Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -quiet -p xc2s100-tq144-5 -cm area
-detail -ignore_keep_hierarchy -pr b -r -k 4 -c 100 -tx off -o main_map.ncd
main.ngd main.pcf
Target Device : x2s100
Target Package : tq144
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.4 $
Mapped Date : Tue Sep 16 13:54:09 2003

Design Summary
--------------
Number of errors: 1
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,108 out of 2,400 46%
Number of 4 input LUTs: 2,279 out of 2,400 94%
Logic Distribution:
Number of occupied Slices: 1,281 out of 1,200
106%
(OVERMAPPED)
Number of Slices containing only related logic: 978 out of 1,281
76%
Number of Slices containing unrelated logic: 303 out of 1,281
23%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number 4 input LUTs: 2,432 out of 2,400 101% (OVERMAPPED)
Number used as logic: 2,279
Number used as a route-thru: 153
Number of bonded IOBs: 54 out of 92 58%
IOB Flip Flops: 32
Number of Tbufs: 416 out of 1,280 32%
Number of Block RAMs: 5 out of 10 50%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 2 out of 4 50%

Total equivalent gate count for design: 108,827
Additional JTAG gate count for IOBs: 2,688

--
Lorenzo

 

[Jake Janovetz]

In-maintenance folks have supposedly been receiving 6.1i since the
beginning of September. I received mine on Monday. Since I work from
both a laptop and desktop, I decided to try it on the laptop and see
how the performance compared. I haven't done much in-depth.

Jake


antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309152346.7e1ed7f5@posting.google.com>...

jakespambox@yahoo.com (Jake Janovetz) wrote in message news:<d6ad3144.0309151854.54e599c2@posting.google.com>...
Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled
it under 6.1i (from 5.2i, previously). It failed timing by about 20%
where it previously passed.

Anyone have similar "luck" ?

Jake

where did you get 6.1i ? dont see it been released on xilinx website?
antti

 

[Jake Janovetz]

Guiseppe-

This was with SP1 (as you mentioned later) applied. I find it
interesting that there is a service pack available by the time I
receive my first media.

Why would I have to regenerate with PACE? I do this stuff by hand, so
I've never used PACE. Is there some intermediate file that it updates
now? The constraints file does contain placement and pin locations,
but those seem to be followed as is indicated by the post-PR floorplan
look. (and FPGA editor)

Jake


"Giuseppeł" <miaooaim@inwind.it> wrote in message news:<bk6kph$qb16m$1@ID-61213.news.uni-berlin.de>...

Had you regenerate the ucf file with PACE?
I regenerate copletely this file and the time constrain return to the
original (5.2 version)

Bye
Giuseppe

"Jake Janovetz" <jakespambox@yahoo.com> ha scritto nel messaggio
news:d6ad3144.0309151854.54e599c2@posting.google.com...
Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled
it under 6.1i (from 5.2i, previously). It failed timing by about 20%
where it previously passed.

Anyone have similar "luck" ?

Jake

 

[rickman]

Jake Janovetz wrote:

Guiseppe-

This was with SP1 (as you mentioned later) applied. I find it
interesting that there is a service pack available by the time I
receive my first media.

Why would I have to regenerate with PACE? I do this stuff by hand, so
I've never used PACE. Is there some intermediate file that it updates
now? The constraints file does contain placement and pin locations,
but those seem to be followed as is indicated by the post-PR floorplan
look. (and FPGA editor)

Jake

Don't be surprised about the service packs. The "features" that are
part of each release are planned well in advance. When bugs are
encountered, they priortize them and only fix the "critical" bugs prior
to release. The lesser bugs and other features are then planned into
later releases, again according to priority.

A conversation I had with a Xilinx person indicated that they have bug
fixes and new features planned at least two service packs ahead. I
think it is pretty good that Xilinx was able to release the first
service pack so soon. To me this shows that they did a good job of
triage, planning and execution on both the 6.1 release and the first
service pack.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Tullio Grassi]

Anyway, I would rather reduce by a factor of 2 the releases
and service packs, if this reduce the bugs.

Tullio

On Tue, 16 Sep 2003, rickman wrote:

Don't be surprised about the service packs. The "features" that are
part of each release are planned well in advance. When bugs are
encountered, they priortize them and only fix the "critical" bugs prior
to release. The lesser bugs and other features are then planned into
later releases, again according to priority.

A conversation I had with a Xilinx person indicated that they have bug
fixes and new features planned at least two service packs ahead. I
think it is pretty good that Xilinx was able to release the first
service pack so soon. To me this shows that they did a good job of
triage, planning and execution on both the 6.1 release and the first
service pack.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

---------

 

[Antonio]

Lorenzo visto che sei italiano colgo l'opportunitŕ per scriverti nella nostra lingua. <BR>
Sto facendo un lavoro di tesi riguardante la riconfigurazione parziale dei dispositivi che sfruttano questa funzionalitŕ e avendo preso come riferimento <BR>
l'applnote290 di xilinx ho utilizzato un loro esempio per indirizzarmi, solo che ora sono bloccato perchč non riesco a risolvere un problema che incontro e cioč nell'operazione di sintesi i seguenti 2 errori: <BR>
error 3317Library synplify not found <BR>
error 3013Library synplify not declared <BR>
Per favore puoi aiutarmi? <BR>
Grazie Antonio <BR>
P.S.:dimenticavo, la mia versione di software č la 5.2i(ise).