Xilinx ISE 6.1i DCM is dead

[Patrik Eriksson]

The 6.1i/6.1i SP1 unisim DCM model doesn't work in a simulation that
works with the model included in 5.2i SP3. Has anyone else experience
the same problem? What has been changed? Why is the model changed?

/Patrik Eriksson

 

[gerard Thierry]

"Patrik Eriksson" <patrik.eriksson@netinsight.net> a écrit dans le message
de news:3F68229C.8040806@netinsight.net...

The 6.1i/6.1i SP1 unisim DCM model doesn't work in a simulation that
works with the model included in 5.2i SP3. Has anyone else experience
the same problem? What has been changed? Why is the model changed?

/Patrik Eriksson

Unisim DCM model is change and now the RST signal must be asserted for 3
CLKIN clock cycles.
A test exists in VITAL model to print a message if the timing is not correct
but the test doesn't work
at "power up" because a signal is not correctly initialized.

To make this working, do the folowing modifications.

in "unisim_VITAL.vhd" and "simprim_VITAL_mti.vhd" files
replace all occurences of the folowing line
signal rst_reg : std_logic_vector(2 downto 0);
by :
signal rst_reg : std_logic_vector(2 downto 0) := "000";
and compile the modified files.

Now the simulation must generate an error like:
# ** Error: Timing Violation Error : RST on instance * must be asserted for
3 CLKIN clock cycles.
# Time: 30 ns Iteration: 3 Instance: /testbench/u_2/dcm_i

Gerard Thierry