Xilinx ISE 4.2 Unisim Block RAM bug?

K

Kevin Brace

Guest
Hello,

I developed my own synchronous FIFO buffer using Virtex Block RAM.
However, when I try to simulate it on ModelSim XE 5.5e and 5.7c with ISE
WebPACK 4.2's Unisim library, I get the following error messages.

# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:690 ns, posedge
CLKB &&& clkb_enable:690 ns, 100 ps );
# Time: 690 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:690 ns, posedge
CLKB &&& clkb_enable:690 ns, 100 ps );
# Time: 690 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:720 ns, posedge
CLKB &&& clkb_enable:720 ns, 100 ps );
# Time: 720 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:720 ns, posedge
CLKB &&& clkb_enable:720 ns, 100 ps );
# Time: 720 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:750 ns, posedge
CLKB &&& clkb_enable:750 ns, 100 ps );
# Time: 750 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:750 ns, posedge
CLKB &&& clkb_enable:750 ns, 100 ps );
# Time: 750 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0
.
.
.
.
.


The above error messages were displayed when the FIFO contains
one entry, and the user logic tried to do simultaneous read/write of the
FIFO.
But if the FIFO contains two or more entries, simultaneous read/write of
the FIFO doesn't display the above error message, and the FIFO functions
correctly.
When the FIFO's RAM (Virtex Block RAM in dual-port mode.) is replaced
with Verilog's generic RAM, the FIFO functions correctly, so at this
point I suspect that something is wrong with Unisim's Virtex Block RAM.
Next thing I tried was to simulate synchronous version of a FIFO
buffer (fifoctlr_cc.v) in Xilinx Application Note 175 with the same
testbench code I used for testing my own FIFO.
Interestingly, I got error messages very similar to what I got with my
own FIFO.

# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374):
$recovery( posedge CLKB:690100 ps,
posedge CLKA &&& clka_enable:690100 ps, 100 ps );
# Time: 660100 ps Iteration: 1 Instance:
/fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374):
$recovery( posedge CLKB:720100 ps,
posedge CLKA &&& clka_enable:720100 ps, 100 ps );
# Time: 720100 ps Iteration: 1 Instance:
/fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1
# ** Error:
.../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374):
$recovery( posedge CLKB:750100 ps,
posedge CLKA &&& clka_enable:750100 ps, 100 ps );
# Time: 750100 ps Iteration: 1 Instance:
/fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1
.
.
.
.
.


The application note doesn't say that fifoctlr_cc.v cannot
handle simultaneous read/write, so I am not sure why these error
messages get displayed.
Eventually I ran out of ideas, so I decided to try ISE 5.1's Unisim
library, and somehow this time the both FIFOs functioned correctly.
Am I doing something I am not supposed to do with Virtex's Block RAM, or
did Unisim's Virtex Block RAM contained a bug until the release of ISE
5.1 (Virtex was released in 1998)?



Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
 
http://support.xilinx.com/techdocs/1655.htm


Kevin Brace wrote:

Hello,

I developed my own synchronous FIFO buffer using Virtex Block RAM.
However, when I try to simulate it on ModelSim XE 5.5e and 5.7c with ISE
WebPACK 4.2's Unisim library, I get the following error messages.

# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:690 ns, posedge
CLKB &&& clkb_enable:690 ns, 100 ps );
# Time: 690 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:690 ns, posedge
CLKB &&& clkb_enable:690 ns, 100 ps );
# Time: 690 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:720 ns, posedge
CLKB &&& clkb_enable:720 ns, 100 ps );
# Time: 720 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:720 ns, posedge
CLKB &&& clkb_enable:720 ns, 100 ps );
# Time: 720 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:750 ns, posedge
CLKB &&& clkb_enable:750 ns, 100 ps );
# Time: 750 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453):
$recovery( posedge CLKA:750 ns, posedge
CLKB &&& clkb_enable:750 ns, 100 ps );
# Time: 750 ns Iteration: 2 Instance:
/FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0
.
.
.
.
.


The above error messages were displayed when the FIFO contains
one entry, and the user logic tried to do simultaneous read/write of the
FIFO.
But if the FIFO contains two or more entries, simultaneous read/write of
the FIFO doesn't display the above error message, and the FIFO functions
correctly.
When the FIFO's RAM (Virtex Block RAM in dual-port mode.) is replaced
with Verilog's generic RAM, the FIFO functions correctly, so at this
point I suspect that something is wrong with Unisim's Virtex Block RAM.
Next thing I tried was to simulate synchronous version of a FIFO
buffer (fifoctlr_cc.v) in Xilinx Application Note 175 with the same
testbench code I used for testing my own FIFO.
Interestingly, I got error messages very similar to what I got with my
own FIFO.

# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374):
$recovery( posedge CLKB:690100 ps,
posedge CLKA &&& clka_enable:690100 ps, 100 ps );
# Time: 660100 ps Iteration: 1 Instance:
/fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374):
$recovery( posedge CLKB:720100 ps,
posedge CLKA &&& clka_enable:720100 ps, 100 ps );
# Time: 720100 ps Iteration: 1 Instance:
/fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1
# ** Error:
../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374):
$recovery( posedge CLKB:750100 ps,
posedge CLKA &&& clka_enable:750100 ps, 100 ps );
# Time: 750100 ps Iteration: 1 Instance:
/fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1
.
.
.
.
.


The application note doesn't say that fifoctlr_cc.v cannot
handle simultaneous read/write, so I am not sure why these error
messages get displayed.
Eventually I ran out of ideas, so I decided to try ISE 5.1's Unisim
library, and somehow this time the both FIFOs functioned correctly.
Am I doing something I am not supposed to do with Virtex's Block RAM, or
did Unisim's Virtex Block RAM contained a bug until the release of ISE
5.1 (Virtex was released in 1998)?



Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Click to expand...
 
Hi Paulo,

Thanks for the link.
This part of the Answers Database sounds relevant to my problem.
_______________________________________________________________________________
If one port attempts to read from the same memory cell to which the
other is

simultaneously writing (also violating the clock setup requirement) the
write will be

successful, but the data read will be invalid.
_______________________________________________________________________________

However, the information provided doesn't solve the problem I am
having.
Looking at the error messages and the wave form, it seems to me I will
have to put some kind of delay (I believe that's called Tbccs.) between
Port A's write access to address x on clock cycle y and Port B's read
access to address x on clock cycle y + 1, but since I am implementing a
synchronous FIFO that allows simultaneous read/write (push/pop), I don't
see how I am going to do that for a FIFO that is synthesizable.
Am I going to have to delay the reading by one clock cycle (Performing
read access to Port B on clock cycle y + 2)?
I don't see that as a practical solution.
Also, the above link still doesn't explain why the FIFO fails with ISE
4.2's Unisim

library, but works fine with ISE 5.1 and 5.2's Unisim library.


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so

within the newsgroup.)
 
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