Xilinx ISE 12.3 : library simprim problem

[neosis]

Hi all, I'm using ISE 12.3 to implement a design.
I generate a verilog netlist which contains cells of the simprim library.
I used this command line to do that :
netgen -w -ecn conformal -ne -mhf clockbuf
I obtained 2 verilog files : glbl.v & clockbuf_ecn.v

Then I take this netlist and do some changes on it ( split it in parts fo
example ). But if I start a new project whith the new files, ise can't fin
simprims library.

I tried also to start another new project with these 2 files( wit
nochanges), and I included all verilog files of used cells from the simpri
library. and here is what I obtain :

ERROR:HDLCompilers:244
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 3
Name 'glbl.GTS' could not be resolved
ERROR:HDLCompilers:185
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 3
Illegal right hand side of continuous assign
ERROR:HDLCompilers:244
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 4
Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 4
Illegal right hand side of continuous assign
ERROR:HDLCompilers:244
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" lin
46 Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" lin
46 Illegal right hand side of continuous assign

Can anyone explain me what to do?
thx for your help.



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[neosis]

Hi all, I'm not sure that I asked the best question. Here it is : If
implement any design with ISE, then I use netgen to generate a new verilo
netlist (lets call it newNet.v), can I take "newNet.v" and start a ne
project with it or not?
I do not want to run simulation but I want to implement "newNet.v" an
synthesize it with XST.
The problem now is that "newNet.v" uses SIMPRIM files and "glbl.v" when
use these options with netgen :
netgen -w -ecn conformal -ne -mhf clockbuf

I looked in the code provided by xilinx, and i found that it i
instantiated as follows :
tri0 GSR = glbl.GSR; // in X_FF.v for example

And the errors are like this :
ERROR:HDLCompilers:244
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 4
Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 4
Illegal right hand side of continuous assign

I read in xilinx forum that glbl is only used for simulation !!! That why
want tu use another library for synthesis.
Any ideas? Thx again for your help.

---------------------------------------
Posted through http://www.FPGARelated.com

 

On Monday, 18 October 2010 17:04:55 UTC+5:30, neosis wrote:

Hi all, I'm using ISE 12.3 to implement a design.
I generate a verilog netlist which contains cells of the simprim library.
I used this command line to do that :
netgen -w -ecn conformal -ne -mhf clockbuf
I obtained 2 verilog files : glbl.v & clockbuf_ecn.v

Then I take this netlist and do some changes on it ( split it in parts for
example ). But if I start a new project whith the new files, ise can't find
simprims library.

I tried also to start another new project with these 2 files( with
nochanges), and I included all verilog files of used cells from the simprim
library. and here is what I obtain :

ERROR:HDLCompilers:244 -
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 36
Name 'glbl.GTS' could not be resolved
ERROR:HDLCompilers:185 -
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 36
Illegal right hand side of continuous assign
ERROR:HDLCompilers:244 -
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42
Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185 -
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42
Illegal right hand side of continuous assign
ERROR:HDLCompilers:244 -
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" line
46 Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185 -
"../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" line
46 Illegal right hand side of continuous assign

Can anyone explain me what to do?
thx for your help.



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Posted through http://www.FPGARelated.com

I am facing the same problem. Did you figure out how to resolve this problem?