Xilinx: infering dual port ROM in VHDL

[sebastian]

hi,

im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can
infer dual port RAM, but i need it to be ROM in order to have it
initialised. does anybody know how to do it? i've been searching the
web and xilinx website, but i havent seen how to infer a dual port
ROM, only regular ROM, but i need to do two read access (and given
that the ROMs will be implemented in BlockRAM, it'd be a waste if i
had to use two cycles to read from dual port capable BlockRAMs)
i'd like the approach to be VHDL, cause it seems that you can do it
with Coregen?? but i want it to be VHDL cause the ROM generation has
to automatic (thru a C program that generates VHDL code)
comments are welcome, TIA

 

[John Adair]

It does not have to be ROM to be initialised. I usually use constraints
editor or go directly to the ucf file to set the RAM/ROM initial values. The
blockram can be considered as writeable ROM that simply isn't written.
Usually I tie off the write enable to the inactive state if it really
matters but more often being able to split the blockram into a combination
of RAM and pseudo ROM is more useful to me.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"sebastian" <malaka@email.it> wrote in message
news:6aefd6be.0406110137.58a0268f@posting.google.com...

hi,

im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can
infer dual port RAM, but i need it to be ROM in order to have it
initialised. does anybody know how to do it? i've been searching the
web and xilinx website, but i havent seen how to infer a dual port
ROM, only regular ROM, but i need to do two read access (and given
that the ROMs will be implemented in BlockRAM, it'd be a waste if i
had to use two cycles to read from dual port capable BlockRAMs)
i'd like the approach to be VHDL, cause it seems that you can do it
with Coregen?? but i want it to be VHDL cause the ROM generation has
to automatic (thru a C program that generates VHDL code)
comments are welcome, TIA

 

[Ray Andraka]

Inference doesn't work for this case on any tool that i am aware of. You
can instantiate dual port RAMs, initialize them with the init=attributes
and generics (latest synplify generates the attributes from the generic).
For ROM, just tie the write enables to '0'.

sebastian wrote:

hi,

im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can
infer dual port RAM, but i need it to be ROM in order to have it
initialised. does anybody know how to do it? i've been searching the
web and xilinx website, but i havent seen how to infer a dual port
ROM, only regular ROM, but i need to do two read access (and given
that the ROMs will be implemented in BlockRAM, it'd be a waste if i
had to use two cycles to read from dual port capable BlockRAMs)
i'd like the approach to be VHDL, cause it seems that you can do it
with Coregen?? but i want it to be VHDL cause the ROM generation has
to automatic (thru a C program that generates VHDL code)
comments are welcome, TIA

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
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