Xilinx FPGA one project loadable, another not - any hint?

Hi,


I do not know if this matters: it is a Spartan IIe 50k device, interfaces
are - or JTAG or parallel.

One project, a small test vhdl code, can be loaded and works correct. Both
ways JTAG and parallel are possible.

Another larger project cannot be loaded.
The Impact-Loader says after 'loading' that the 'done-pin does not go
high'. Indeed the done-pin remains low, also when loading via parallel
interface via microprocessor.

The BIT-file which is used in any of the cases, was compiled with ISE 4.2i
as well as with the newest WebPack 6.2.02i

Any hint how a compiled file can be wrong so the BIT-file cannot be
loaded?


Klaus Hiltrop

 

[Andreas Hölscher]

khiltrop@gesytec.de wrote:

Hi,


I do not know if this matters: it is a Spartan IIe 50k device, interfaces
are - or JTAG or parallel.

One project, a small test vhdl code, can be loaded and works correct. Both
ways JTAG and parallel are possible.

Another larger project cannot be loaded.
The Impact-Loader says after 'loading' that the 'done-pin does not go
high'. Indeed the done-pin remains low, also when loading via parallel
interface via microprocessor.

The BIT-file which is used in any of the cases, was compiled with ISE 4.2i
as well as with the newest WebPack 6.2.02i

Any hint how a compiled file can be wrong so the BIT-file cannot be
loaded?
Either use a pullup resistor on DONE or configure the BIT-File to drive

the DONE pin high (Startup Options in Generate Programming File Properties)

Klaus Hiltrop