XILINX FPGA: DCM locked Signal

[Muthu]

Hi,

Is the locked signal of DCM, is synchronous / Asynchronous ?

Regards,
Muthu

 

[Austin Lesea]

Muthu,

It is generated on the rising edge of CLKIN -- synchronous.

Austin

Muthu wrote:

Hi,

Is the locked signal of DCM, is synchronous / Asynchronous ?

Regards,
Muthu

 

[Tullio Grassi]

So is possible the situation desscribed below ?

- the DCM is locked on an input clock;
- I stop completly the clock (from outside the FPGA),
- the DLL looses lock, but the LOCKED signal is
never updated and remain high

I think I observed something like that.
If it is correct, it's a disturbing feature.

Tullio


On Fri, 5 Dec 2003, Austin Lesea wrote:

Muthu,

It is generated on the rising edge of CLKIN -- synchronous.

Austin

Muthu wrote:
Is the locked signal of DCM, is synchronous / Asynchronous ?

 

[Austin Lesea]

Tullio,

That is what the status bit "CLK_IN_STOPPED" is for.

Austin

Tullio Grassi wrote:

So is possible the situation desscribed below ?

- the DCM is locked on an input clock;
- I stop completly the clock (from outside the FPGA),
- the DLL looses lock, but the LOCKED signal is
never updated and remain high

I think I observed something like that.
If it is correct, it's a disturbing feature.

Tullio


On Fri, 5 Dec 2003, Austin Lesea wrote:


Muthu,

It is generated on the rising edge of CLKIN -- synchronous.

Austin

Muthu wrote:

Is the locked signal of DCM, is synchronous / Asynchronous ?