Xilinx FPGA Clocking resources and design implementation.

[Stefano Moser]

Hi all,
I'm designing a board with a Xilnx Spartan 6 LX16, and I've some
questions about clock managing and pin-planning, before the complete
netlist/implementation being prepared.

The clock to the FPGA is generated through an oscillator and feed on a
gclk pin of the FPGA. The internal CMT (Clock Management Tile) is then
used to clock an external ADC and two data-buses with the use of
IOSERDES primitives, forwarding clock on one of them. This design will
also include a DDR memory interface. Another clock will come from the
USB interface (located on an external USB bridge).

What are the best practices to follow to correctly pin-planning the most
important pins (I refer to pins that will be used as clock I/O and
forwarding for data busses), without an already defined implementation
of the logic?

Thanks a lot for the help!
Best regards,
Stefano.

 

[Joel Williams]

I'm sure others might have a more informed perspective, but from my
recent personal observations..

The internal CMT (Clock Management Tile) is then used to clock an
external ADC and two data-buses with the use of IOSERDES primitives,
forwarding clock on one of them.

IOSERDES complains a bit about clocks if your bus spans more than one
half bank. Keep it to one if you can, but if your data rate isn't very
high it shouldn't actually be a problem. For reference, I used a 200 MHz
data rate (DDR) ADC and had to span half banks and it works fine. The
only real issue is that the core generator in 12.4 can't produce code
that synthesises and you'll spend a bit more time fiddling with it.

This design will also include a DDR memory interface.

Pin placements are more or less fixed if you want to use MIG, except
that you can swap certain pins as detailed in the data sheet.

Joel

 

[Gabor]

On Thursday, March 3, 2011 5:41:13 AM UTC-5, Stefano Moser wrote:

Hi all,
I'm designing a board with a Xilnx Spartan 6 LX16, and I've some
questions about clock managing and pin-planning, before the complete
netlist/implementation being prepared.

The clock to the FPGA is generated through an oscillator and feed on a
gclk pin of the FPGA. The internal CMT (Clock Management Tile) is then
used to clock an external ADC and two data-buses with the use of
IOSERDES primitives, forwarding clock on one of them. This design will
also include a DDR memory interface. Another clock will come from the
USB interface (located on an external USB bridge).

What are the best practices to follow to correctly pin-planning the most
important pins (I refer to pins that will be used as clock I/O and
forwarding for data buses), without an already defined implementation
of the logic?

Thanks a lot for the help!
Best regards,
Stefano.

Definitely build the MIG core and use its recommended
(in some cases required) pinout. You don't need to have
any other project code to do this, although it helps
to have enough to build a "don't use" list for pins
required by other functions.

Think hard before clocking an ADC with an FPGA output.
Depending on the application you may need better
jitter specs than can be achieved by the FPGA. For
example communications applications typically have
input bandwidth very near the sampling rate and
therefore are very sensitive to sampling clock
jitter. Don't assume that the output jitter from
an FPGA pin will be as good as the jitter spec
on the internal DCM or PLL. There are other
sources of jitter, including activity on nearby
pins, and they are all additive.

-- Gabor

 

[Mike Shogren]

Stefano,

I would _strongly_ recommend stubbing out the top level with all of
the pins in the design, especially the "picky" ones that you pointed
out. It may take some time up front, but well worth it not to get
burned with a bad pin placement that cripples your design once you get
boards back. You should not need the entire design completed, but you
will need some logic in place to ensure that things don't get
synthesized out by the tools.

Regarding the comment about clocking the ADC with an FPGA output...
This assumes that the FPGA-driven clock drives the sample rate of the
ADC. Depending on what you need, performance-wise, this may still be
fine. Something to keep in mind though, for sure.

Good luck!
--
Mike Shogren
Director of FPGA Development
Epiq Solutions
www.epiq-solutions.com

 

[Stefano Moser]

Thank you all for the replies,
I think I will go with what Mike suggests.
Regarding the ADC, I was aware of the poor performances of the FPGAs
regarding clock jitter, so it's all ok for the performances we need.
Thanks again!

Stefano.

Mike Shogren wrote:

Stefano,

I would _strongly_ recommend stubbing out the top level with all of
the pins in the design, especially the "picky" ones that you pointed
out. It may take some time up front, but well worth it not to get
burned with a bad pin placement that cripples your design once you get
boards back. You should not need the entire design completed, but you
will need some logic in place to ensure that things don't get
synthesized out by the tools.

Regarding the comment about clocking the ADC with an FPGA output...
This assumes that the FPGA-driven clock drives the sample rate of the
ADC. Depending on what you need, performance-wise, this may still be
fine. Something to keep in mind though, for sure.

Good luck!
--
Mike Shogren
Director of FPGA Development
Epiq Solutions
www.epiq-solutions.com