Xilinx Flash PROM and Config rate for Spartan 6 FPGA

[Aditi]

Hi All,



I am using a Spartan-6 FPGA in my design (XC6SLX16 -2CSG225).

I am using a XILINX Serial Flash PROM (XC40FS) to boot the FPGA.



Note : The size of my bit file is about 454KB ~ 3.5M bit.



My concern is: Initially I have used a 2MHz CCLK as the ConfigRate

and the time it took for the PROM to boot the FPGA was about 2sec

(measured it on the scope).



Then I increased the CCLK to be about 10MHz, and the time taken to
boot the

FPGA decreased to 0.7sec.

And if I increase the rate anything more than 10MHz ( the max I can
see is 26MHz),

the boot time does not have any effect and remains at 0.7sec.

Does the PROM take so long to boot the FPGA?



Also, when I look at the datasheet for the PROM (XC40FS), the min
clock period

it could take was about 100ns i.e the max CCLK frequency would be
10MHz.

But when I tried to use a ConfigRate of 26MHz, the FPGA still booted
(and took the same

time about 0.7sec). Does this mean the PROM does something with the
clock if it higher than it can handle?



Also, I do not have a lot of logic in my Verilog project but still

the .bit file is about 3.5M bit.

Is the file size very normal? Or am I missing something here?

Can I compress the bit file?



Thanks,

Regards,

Aditi
Embedded Systems Engineer
Signalogic Inc

 

[Christopher Head]

On Tue, 14 Dec 2010 15:43:32 -0800 (PST)
Aditi <aditi.groups@gmail.com> wrote:

[snip]

Also, I do not have a lot of logic in my Verilog project but still

the .bit file is about 3.5M bit.

Is the file size very normal? Or am I missing something here?

Can I compress the bit file?

I'm not familiar with S6, but with S3A, there's a "-g Compress" option
you can pass to the bitgen utility to make a smaller bitstream. Sorry,
don't know anything about how to do it in the graphical environment if
you're using that. How much difference that will make is of course a
subject for your own experiments, but it's a trivial first thing to try!

Chris