xilinx fir compiler

[kaz]

I have used altera DSPBuilder for several multichannel multirate filter
designs.
I have heard that xilinx fir compiler(latest one possibly) can process
multichannels even if they have different input sampling rates on sam
single
path.

Is that true?

There is another restriction with altera upsampling fir: The input sample
must
not be applied in immediate succession i.e. samples must be dispersed apar
to
give room to new samples at output. Does this apply to xilinx fir compile
as
well.

Thanks in advance

Kaz



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[Benjamin Couillard]

The best way to find out is to simulate the an instantiated core with Modelsim or Active-HDL or any other simulator.

About the upsampling FIR : If the processing clock is 100 MHz, the input sample rate is 50 MHz and the ouput sample rate. Then by definition, you can only have one new input sample every other clock cycle.

 

[kaz]

About the upsampling FIR : If the processing clock is 100 MHz, the inpu
sample rate is 50 MHz and the ouput sample rate. Then by definition, yo

can only have one new input sample every other clock cycle.
That is true but I might have my input samples coming in at 100 MHz say a
pairs of sample1 then 2 then two invalid clocks valid pattern of 1100.
instead of 1010.

Thanks

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[Benjamin Couillard]

I need more information. What core version, how many taps?

Anway like I said before, the best way is to simulate the design in Modelsim. Try the impulse response, step response, white noise, chirp response, etc. and compare the results to the one you would get in Matlab (or Octave).

 

[kaz]

I need more information. What core version, how many taps?

Anway like I said before, the best way is to simulate the design i
Modelsim. Try the impulse response, step response, white noise, chir

response, etc. and compare the results to the one you would get in Matla
(or Octave).
I have been doing altera dspbuilder for over two years now and I got
extremely impressed by its accuracy, resource usage, speed and above al
the
ease of multichannel multirate performance. I am now asked to move t
xilinx
system generator and was told it is even better. But frankly I am shocke
and
bewildered that their data control for multichannel/multirate systems i
so
complicated and demanding extra glue logic. For example it turned out tha

you will need to check if a module is ready or not for input or else
regularise the input stream in order to avoid this check. Additionall
there
is an output named channel_in !! to let you check if a module is read
specifically for that channel. This interface is bewildering compared to
altera dspbuilder. The difference is astronomical. I know xilinx starte
the
idea of automation. Am I missing something??

With altera dspbuilder you can produce chains of several modules at
click, that would otherwise require months of design work. such chains ca
be
updated readily provided the designer hasn't added too much glue. Yet with
xilinx approach it looks I have to spend days or weeks to arrange for th
glue logic and thus becomes difficult to update. I hope I am wrong. I wil
be
glad if anyone can tell me if there is an easier way to use sysgen block
that I am missing, in particular the fir compiler(say version 5.0)
Thanks.

Kaz



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[kaz]

Finally sorted out. To be fair to Xilinx SysGen I realised it is lack of
adequate documentation and some misleading terminolgy plus the effect o
moving
from Altera DSPBuilder to SysGen.

I managed to get equivalent performance on FIR compiler and here are the
differences that caused confusion:

1) Say I wanted a filter for 4 channels, clock speed 320MHz, sample rate o

each channel is 10Msps. In DSPBuilder I can send my 4 channels as
11110000...11110000... In SysGen I have to spread them as
1000..1000..1000..1000.. as this will match the ready state which then ca
be
ignored.

2) SysGen asks to enter sample period. In fact this turns out not to be th
period of 10Msps but the net time folding factor i.e. 320/10/4 = 8
Altera asks to enter 320MHz for sys clk and 10Msps for input rat
directly.

Kadhiem

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